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Following the elapse of (×0) µs or more after the SWE1 bit is set to 1 in FLMCR1, 128-byte
program data is stored in the program data area and reprogram data area, and the 128-byte data in
the program data area in RAM is written consecutively to the program address (the lower 8 bits of
the first address written to must be H'00 or H'80). 128 consecutive byte data transfers are
performed. The program address and program data are latched in the flash memory. A 128-byte
data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must
be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup)
is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of (y) µs or more, the
operating mode is switched to program mode by setting the P1 bit in FLMCR1. The time during
which the P1 bit is set is the flash memory programming time. Refer to the table in figure 22-11
for the programming time.
22.7.2
Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of the given programming time, clear the P1 bit in FLMCR1, then wait for at least
(α) µs before clearing the PSU1 bit to exit program mode. After the elapse of at least (β) µs, the
watchdog timer is cleared and the operating mode is switched to program-verify mode by setting
the PV1 bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data
should be made to the addresses to be read. The dummy write should be executed after the elapse
of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units),
the data at the latched address is read. Wait at least (ε) µs after the dummy write before
performing this read operation. Next, the originally written data is compared with the verify data,
and reprogram data is computed (see figure 22-11) and transferred to RAM. After verification of
128 bytes of data has been completed, exit program-verify mode, wait for at least (η) µs, then
clear the SWE1 bit in FLMCR1. If reprogramming is necessary, set program mode again, and
repeat the program/program-verify sequence as before. The maximum number of repetitions of the
program/program-verify sequence is indicated by the maximum programming count (N).
However, ensure that the program/program-verify sequence is not repeated more than (N) times on
the same bits.
Notes on Program/Program-Verify Procedure
1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must
be H'00 or H'80.
2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer
should be used.
807
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