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ISR—IRQ Status Register
Bit
:
IRQ7F
Initial value
:
R/W
:
R/(W)*
IRQ7 to IRQ0 flag
0
1
Note: * Only 0 can be written to these bits (to clear these flags).
1032
7
6
IRQ6F
IRQ5F
0
0
R/(W)*
R/(W)*
[Clearing]
(1) Writing 0 to flag IRQnF after reading IRQnF=1;
(2) When interrupt exception processing is executed when set for LOW-level detection
(IRQnSCB=IRQnSCA=0) and, in addition, the IRQn input level is HIGH;
(3) When IRQn interrupt exception processing is executed when set for rising edge or
falling edge or both rising edge and falling edge detection (IRQnSCB=1 and
IRQnSCA=1);
(4) When the DTC starts due to IRQn interrupt and the DTC MRB DISEL bit is 0.
[Setting]
(1) When the IRQn input level changes to LOW when set for LOW level detection
(IRQnSCB=IRQnSCA=0);
(2) When a falling edge occurs at the IRQn input when set for falling edge detection
(IRQnSCB=0, IRQnSCA=1);
(3) When a rising edge occurs at the IRQn input when set for rising edge detection
(IRQnSCB=1, IRQnSCA=0);
(4) When either a falling edge or rising edge occurs at the IRQn input when set for both
falling edge and rising edge detection (IRQnSCB=IRQnSCA=1).
H'FE15
5
4
IRQ4F
IRQ3F
0
0
R/(W)*
R/(W)*
Interrupt Controller
3
2
IRQ2F
IRQ1F
0
0
R/(W)*
R/(W)*
1
0
IRQ0F
0
0
R/(W)*
(n= 7 to 0)
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