Hitachi H8S/2633 Hardware Manual page 580

1. OS = 0 (DADR corresponds to T
a. CFS = 0 [base cycle = resolution (T) × 64]
t
f1
t
L1
t = t = t = · · · = t
f1 f2 f3
t + t + t + · · · + t
L1 L2 L3
b. CFS = 1 [base cycle = resolution (T) × 256]
t
f1
t
L1
t = t = t = · · · = t
f1 f2 f3
t + t + t + · · · + t
L1 L2 L3
560
)
L
1 conversion cycle
t
f2
t t
L2 L3
= T × 64
= t
f255 f256
+ t = T
L255 L256 L
Figure 14-4 (1) Output Waveform
1 conversion cycle
t
f2
t t
L2 L3
= T × 256
= t
f63 f64
+ t = T
L63 L64 L
Figure 14-4 (2) Output Waveform
t
f255
t t
L255 L256
t
f63
t t
L63 L64
t
f256
t
f64