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10.8.2
Register Configuration
Table 10-12 shows the port B register configuration.
Table 10-12 Port B Registers
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Port B open-drain control register
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
Bit
:
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value :
R/W
:
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode. The OPE bit in SBYCR is used to select
whether the address output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
• Modes 4 to 6
The corresponding port B pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of the PBDDR bits. When pins are not used as
address outputs, setting a PBDDR bit to 1 makes the corresponding port B pin an output port,
while clearing the bit to 0 makes the pin an input port.
• Mode 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
370
7
6
0
0
W
W
Abbreviation
R/W
PBDDR
W
PBDR
R/W
PORTB
R
PBPCR
R/W
PBODR
R/W
5
4
0
0
W
W
Initial Value
H'00
H'00
Undefined
H'00
H'00
3
2
0
0
W
W
Address*
H'FE3A
H'FF0A
H'FFBA
H'FE41
H'FE48
1
0
0
0
W
W
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