Advertisement
7.4.4
Basic Timing
8-Bit 2-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states cannot be inserted.
Note: n = 0 to 7
162
ø
Address bus
CSn
AS
RD
D15 to D8
Read
D7 to D0
HWR
LWR
Write
D15 to D8
D7 to D0
Figure 7-6 Bus Timing for 8-Bit 2-State Access Space
Bus cycle
T
T
1
2
High
Valid
High impedance
Valid
Invalid
Advertisement
