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SDA
1-7
SCL
S
SLA
2
Table 18-4 I
C Bus Data Format Symbols
Legend
S
Start condition. The master device drives SDA from high to low while SCL is high
SLA
Slave address, by which the master device selects a slave device
R/W
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
A
Acknowledge. The receiving device (the slave in master transmit mode, or the master
in master receive mode) drives SDA low to acknowledge a transfer
DATA
Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or
LSB-first format is selected by bit MLS in ICMR
P
Stop condition. The master device drives SDA from low to high while SCL is high
18.3.2
Master Transmit Operation
2
In I
C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal. The transmission procedure and
operations are described below.
(1) Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX
in STCR, according to the operating mode.
(2) Read the BBSY flag in ICCR to confirm that the bus is free, then set bits MST and TRS to 1 in
ICCR to select master transmit mode. Next, write 1 to BBSY and 0 to SCP. This changes
SDA from high to low when SCL is high, and generates the start condition. The TDRE
internal flag is then set to 1, and the IRIC and IRTR flags are also set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU.
2
(3) With the I
C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame
data following the start condition indicates the 7-bit slave address and transmit/receive
direction. Write the data (slave address + R/W) to ICDR. The TDRE internal flag is then
cleared to 0. The written address data is transferred to ICDRS, and the TDRE internal flag is
set to 1 again. This is identified as indicating the end of the transfer, and so the IRIC flag is
cleared to 0. The master device sequentially sends the transmit clock and the data written to
720
8
9
1-7
R/W
A
Figure 18-5 I
8
9
DATA
A
2
C Bus Timing
1-7
8
9
DATA
A/A
P
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