Hitachi H8S/2633 Hardware Manual page 226

The H8S/2633 Series can release the external bus in response to a bus request from an external

device. In the external bus released state, the internal bus master continues to operate as long as

there is no external access.

If an internal bus master wants to make an external access and when a refresh request occurs in the

external bus released state, it can issue a bus request off-chip.

In external expansion mode, the bus can be released to an external device by setting the BRLE bit

in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2633 Series.

When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the

address bus, data bus, and bus control signals are placed in the high-impedance state, establishing

the external bus-released state.

In the external bus released state, an internal bus master can perform accesses using the internal

bus. When an internal bus master wants to make an external access, it temporarily defers

activation of the bus cycle, and waits for the bus request from the external bus master to be

dropped. Also, when a refresh request occurs in the external bus released state, refresh control is

deferred until the external bus master drops the bus request.

If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external

access and when a refresh request occurs in the external bus released state, the BREQO pin is

driven low and a request can be made off-chip to drop the bus request.

When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the

external bus released state is terminated.

The following shows the order of priority when an external bus release request, refresh request,

and external access by the internal bus master occur simultaneously:

(High) Refresh > External bus release > External access by internal bus master (Low)

(High) Refresh > External bus release (Low)

(High) External bus release > External access by internal bus master (Low)

Note: A refresh can be executed at the same time as external access by the internal bus master.