Advertisement
25.3.1
Clock Timing
Table 25-5 lists the clock timing
Table 25-5 Clock Timing
Condition A: V
CC
V
= 3.3 V to AV
ref
T
= –20°C to +75°C (regular specifications), T
a
specifications)
Condition B: V
CC
V
= 3.3 V to AV
ref
T
= –20°C to +75°C (regular specifications), T
a
specifications)
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Clock oscillator settling
time at reset (crystal)
Clock oscillator settling
time in software standby
(crystal)
External clock output
stabilization delay time
32 kHz clock oscillation
settling time
Sub clock oscillator
frequency
Sub clock (ø
) cycle time t
SUB
= PLLV
= 3.0 V to 3.6 V, PV
CC
, V
CC
SS
= PLLV
= 3.0 V to 3.6 V, PV
CC
, V
CC
SS
Symbol
Min
t
62.5
cyc
t
18
CH
t
18
CL
t
—
Cr
t
—
Cf
t
10
OSC1
t
8
OSC2
t
2
DEXT
t
—
OSC3
f
32.768
SUB
30.5
SUB
= 3.0 V to 5.5 V, AV
CC
= AV
= 0 V, ø = 32.768 kHz, 2 to 16 MHz,
SS
= 4.5 V to 5.5 V, AV
CC
= AV
= 0 V, ø = 32.768 kHz, 2 to 25 MHz,
SS
Condition A
Condition B
16MHz
Max
Min
500
40
—
15
—
15
12
—
12
—
—
10
—
5
—
2
2
—
32.768
30.5
= 3.3 V to 5.5 V,
CC
= –40°C to +85°C (wide-range
a
= 3.3 V to 5.5 V,
CC
= –40°C to +85°C (wide-range
a
25MHz
Max
Unit
500
ns
—
ns
—
ns
5
ns
5
ns
—
ms
—
ms
—
ms
2
s
kHz
µs
Test Conditions
Figure 25-2
Figure 25-3
Figure 24-3
Figure 25-3
889
Advertisement
