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7.2.5
Bus Control Register L (BCRL)
Bit
:
BRLE
Initial value
:
R/W
:
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of
WAIT pin input.
BCRL is initialized to H'08 by a power-on reset and in hardware standby mode. It is not initialized
by a manual reset or in software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
Description
External bus release is disabled. BREQ, BACK and BREQO can be used as I/O ports.
0
1
External bus release is enabled.
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE
Description
BREQO output disabled. BREQO can be used as I/O port.
0
BREQO output enabled.
1
Bit 5—Reserved: This bit cannot be modified and is always read as 0.
Bit 4—OE Select (OES): Selects the CS3 pin as the OE pin.
Bit 4
OES
Description
Uses the CS3 pin as the port or as CS3 signal output
0
1
When only area 2 is set for DRAM, or when areas 2 to 5 are set as
contiguous DRAM space, the CS3 pin is used as the OE pin.
144
7
6
BREQOE
0
0
R/W
R/W
5
4
—
OES
DDS
0
0
—
R/W
R/W
3
2
RCTS
WDBE
1
0
R/W
R/W
1
0
WAITE
0
0
R/W
(Initial value)
(Initial value)
(Initial value)
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