Hitachi H8S/2633 Hardware Manual page 885

Using an External Clock: The PLL circuit requires a time for stabilization. Insert a wait of 2 ms

Software Standby Mode Application Example

Figure 24-3 shows an example in which a transition is made to software standby mode at the

falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI

In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling

edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set

to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.

Software standby mode is then cleared at the rising edge on the NMI pin.

Figure 24-3 Software Standby Mode Application Example

NMI exception

Software standby mode

(power-down mode)

SLEEP instruction

NMI exception

stabilization