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10.5.2
Register Configuration
Table 10-7 shows the port 7 register configuration.
Table 10-7 Port 7 Register Configuration
Name
Port 7 data direction register
Port 7 data register
Port 7 register
Note: * Indicates the lower-place 16 bits of the address.
Port 7 Data Direction Register (P7DDR)
Bit
:
7
P77DDR
Initial value :
0
R/W
:
W
P7DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 7 pin by bit.
Read is disenabled. If a read is carried out, undefined values are read out.
By setting P7DDR to 1, the corresponding port 7 pins become output, and by clearing to 0 they
become input.
P7DDR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode. DMAC, 8-bit timer and SCI
are initialized by a manual reset, so the pin state is determined by the specification of P7DDR and
P7DR.
356
Abbreviation
P7DDR
P7DR
PORT7
6
5
P76DDR
P75DDR
0
0
W
W
R/W
W
R/W
R
4
3
P74DDR
P73DDR
0
0
W
W
Initial Value
Address*
H'00
H'FE36
H'00
H'FF06
Undefined
H'FFB6
2
1
P72DDR
P71DDR
0
0
W
W
0
P70DDR
0
W
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