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4.4
Interrupts
Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and
72 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources
and the number of interrupts of each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer
controller (DTC), DMA controller (DMAC), PC break controller (PBC), A/D converter, and I
bus interface (IIC). Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The
interrupt controller has two interrupt control modes and can assign interrupts other than NMI to
eight priority/mask levels to enable multiplexed interrupt control.
For details of interrupts, see section 5, Interrupt Controller.
Notes:
Numbers in parentheses are the numbers of interrupt sources.
1. When the watchdog timer is used as an interval timer, it generates
2. When refresh timer is used as an interval time, an interrupt request
Figure 4-4 Interrupt Sources and Number of Interrupts
External
interrupts
Interrupts
Internal
interrupts
an interrupt request at each counter overflow.
is generated by compare match.
NMI (1)
IRQ7 to IRQ0 (8)
*1
WDT
(2)
*2
Refresh timer
(1)
TPU (26)
8-bit timer (12)
SCI (20)
DTC (1)
DMAC (4)
PBC (1)
A/D converter (1)
IIC(4) (Option)
2
C
87
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