Hitachi H8S/2633 Hardware Manual page 727

Waiting for transfer, or transfer in progress

[Clearing conditions]

1. When 0 is written in IRIC after reading IRIC = 1

2. When ICDR is written or read by the DTC

(When the TDRE or RDRF flag is cleared to 0)

(This is not always a clearing condition; see the description of DTC operation for

Interrupt requested

[Setting conditions]

C bus format master mode

1. When a start condition is detected in the bus line state after a start condition is

2. When a wait is inserted between the data and acknowledge bit when WAIT = 1

3. At the end of data transfer

4. When a slave address is received after bus arbitration is lost

5. When 1 is received as the acknowledge bit when the ACKE bit is 1

C bus format slave mode

1. When the slave address (SVA, SVAX) matches

2. When the general call address is detected

3. When 1 is received as the acknowledge bit when the ACKE bit is 1

4. When a stop condition is detected

Synchronous serial format

1. At the end of data transfer

2. When a start condition is detected with serial format selected

When any other condition arises in which the TDRE or RDRF flag is set to 1

(when the TDRE flag is set to 1 because of first frame transmission)

(at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th

transmit/receive clock pulse when using wait insertion)

(when the AL flag is set to 1)

(when the ACKB bit is set to 1)

(when the AAS and AASX flags are set to 1)

and at the end of data transfer up to the subsequent retransmission start

condition or stop condition detection

(when the TDRE or RDRF flag is set to 1)

(when FS = 0 and the ADZ flag is set to 1)

and at the end of data transfer up to the subsequent retransmission start

condition or stop condition detection

(when the TDRE or RDRF flag is set to 1)

(when the ACKB bit is set to 1)

(when the STOP or ESTP flag is set to 1)

(when the TDRE or RDRF flag is set to 1)

(Initial value)