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BCRH—Bus Control Register H
Bit
:
ICIS1
Initial value
:
R/W
:
7
6
ICIS0
BRSTRM
1
1
R/W
R/W
Burst cycle select 1
0
1
Burst ROM enable
0
1
Idle cycle insertion 0
0
No idle cycle is inserted when an external read cycle follows
an external write cycle.
1
An idle cycle is inserted when an external read cycle follows
an external write cycle. (Initial value)
Idle cycle insertion 1
0
No idle cycle is inserted when an external read cycle
follows an external read cycle of another area.
1
An idle cycle is inserted when an external read cycle
follows an external read cycle of another area. (Initial value)
RAM type select
RMTS2
RMTS1
0
0
1
1
1
Note: When all areas selected in the DRAM area are set for 8-bit access, the PF2
pin can be used as an I/O port or BREQO or WAIT. When set for contiguous
DRAM the bus widths for areas 2 to 5 and the number of access states
(number of programmable waits) must be set to the same values. Do not
attempt to set combinations other than those shown in the table.
H'FED4
5
4
BRSTS1
BRSTS0
0
1
R/W
R/W
Burst cycle = 1 state.
Burst cycle = 2 states.
Area 0 is basic bus interface. (Initial value)
Area 0 is burst ROM interface.
Burst cycle select 0
0
1
RMTS0
Area 5
0
1
0
Normal area
1
1
3
2
RMTS2
RMTS1
0
0
R/W
R/W
Burst access = 4 words max.
Burst access = 8 words max.
Area 4
Area 3
Normal area
Normal area
DRAM area
DRAM area
Contiguous DRAM area
Bus Controller
1
0
RMTS0
0
0
R/W
R/W
Area 2
DRAM area
1069
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