Hitachi H8S/2633 Hardware Manual page 120

Pin Configuration

Table 5-1 summarizes the pins of the interrupt controller.

Interrupt Controller Pins

Nonmaskable interrupt

External interrupt

requests 7 to 0

Table 5-2 summarizes the registers of the interrupt controller.

Interrupt Controller Registers

System control register

IRQ sense control register H

IRQ sense control register L

IRQ enable register

IRQ status register

Interrupt priority register A

Interrupt priority register B

Interrupt priority register C

Interrupt priority register D

Interrupt priority register E

Interrupt priority register F

Interrupt priority register G

Interrupt priority register H

Interrupt priority register I

Interrupt priority register J

Interrupt priority register K

Interrupt priority register L

Interrupt priority register O

Notes: 1. Lower 16 bits of the address.

2. Can only be written with 0 for flag clearing.

IRQ7 to IRQ0 Input

Abbreviation

Nonmaskable external interrupt; rising or

falling edge can be selected

Maskable external interrupts; rising, falling, or

both edges, or level sensing, can be selected

Initial Value