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Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11-46
shows the timing for status flag clearing by the CPU, and figure 11-47 shows the timing for status
flag clearing by the DTC or DMAC.
ø
Address
Write signal
Status flag
Interrupt
request
signal
ø
Address
Status flag
Interrupt
request
signal
Figure 11-47 Timing for Status Flag Clearing by DTC or DMAC Activation
Figure 11-46 Timing for Status Flag Clearing by CPU
TSR write cycle
T1
T2
TSR address
DTC/DMAC
DTC/DMAC
read cycle
write cycle
T1
T2
T1
Destination
Source address
T2
address
483
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