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Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS
Description
0
Specified multiplication factor is valid after transition to software standby mode,
watch mode, and subactive mode
1
Specified multiplication factor is valid immediately after STC bits are rewritten
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master
clock.
Bit 2
Bit 1
SCK2
SCK1
0
0
1
1
0
1
23.2.2
Low-Power Control Register (LPWRCR)
Bit
:
DTON
Initial value :
R/W
:
LPWRCR is an 8-bit readable/writable register that performs power-down mode control. The
following pertains to bits 1 and 0. For details of the other bits, see Section 24.2.3, Low Power
Control Register (LPWRCR). LPWRCR is initialized to H'00 by a power-on reset and in hardware
standby mode. It is not initialized in software standby mode.
Bit 0
SCK0
Description
0
Bus master is in high-speed mode
1
Medium-speed clock is ø/2
0
Medium-speed clock is ø/4
1
Medium-speed clock is ø/8
0
Medium-speed clock is ø/16
1
Medium-speed clock is ø/32
—
—
7
6
LSON
NESEL
0
0
R/W
R/W
5
4
SUBSTP
RFCUT
0
0
R/W
R/W
3
2
—
0
0
R/W
R/W
(Initial value)
(Initial value)
1
0
STC1
STC0
0
0
R/W
R/W
843
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