Advertisement
MCR—Memory Control Register
Bit
:
Initial value
:
R/W
:
Multiplex shift count 1, 0
MXC1
0
1
7
6
TPC
BE
RCDM
0
0
R/W
R/W
R/W
RAS down mode
0
DRAM interface: RAS up mode selected.
1
DRAM interface: RAS down mode selected.
Burst access enable
0
Burst access disabled (permanently full access).
1
DRAM space accessed in high-speed page mode.
TP cycle control
0
One precharge cycle state inserted.
1
Two precharge cycle states inserted.
MXC0
0
8-bit shift
(1) When set for 8-bit access space: Row addresses A23 to A8 are
targets of comparison.
(2) When set for 16-bit access space: Row addresses A23 to A9 are
targets of comparison.
1
9-bit shift
(1) When set for 8-bit access space: Row addresses A23 to A9 are
targets of comparison.
(2) When set for 16-bit access space: Row addresses A23 to A10 are
targets of comparison.
0
10-bit shift
(1) When set for 8-bit access space: Row addresses A23 to A10 are
targets of comparison.
(2) When set for 16-bit access space: Row addresses A23 to A11 are
targets of comparison.
1
—
Refresh cycle wait control 1, 0
H'FED6
5
4
CW2
MXC1
0
0
R/W
R/W
Reserved bit
RLW1
RLW0
0
0
Do not insert wait state.
1
Insert 1 wait state.
1
0
Insert 2 wait states.
1
Insert 3 wait states.
3
2
1
MXC0
RLW1
0
0
0
R/W
R/W
Bus Controller
0
RLW0
0
R/W
1071
Advertisement
