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Bit 5—BUZZ Output Enable (BUZZE): Disenables/enables BUZZ output of PF1 pin. Input
clock of WDT1 selected by PSS, CKS2 to CKS0 bits is output as a BUZZ signal.
Bit 5
BUZZE
Description
0
Functions as PF1 input pin
1
Functions as BUZZ output pin
Bit 4—LCAS Output Pin Selection Bit (LCASS): Selects the LCAS signal output pin.
Bit 4
LCASS
Description
0
Outputs LCAS signal from PF2
1
Outputs LCAS signal from PF6
Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling
of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is
enabled for address output, the address is output regardless of the corresponding DDR setting.
When a pin is disabled for address output, it becomes an output port when the corresponding DDR
bit is set to 1.
72
(Initial value)
(Initial Value)
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