Hitachi H8S/2633 Hardware Manual page 887

Hardware Standby Mode Timing

Figure 24-4 shows an example of hardware standby mode timing.

When the STBY pin is driven low after the RES pin has been driven low, a transition is made to

hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high,

waiting for the oscillation stabilization time, then changing the RES pin from low to high.

CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-

speed mode or sub-active mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR

(WDT1) PSS = 1.

In watch mode, the CPU is stopped and supporting modules other than WDT1 are also stopped.

The contents of the CPUís internal registers, the data in internal RAM, and the statuses of the

internal supporting modules (excluding the SCI, ADC, and 14-bit PWM) and I/O ports are

Figure 24-4 Hardware Standby Mode Timing

stabilization