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24.2.4
Timer Control/Status Register (TCSR)
WDT1 TCSR
Bit
:
Initial value
:
R/W
:
R/(W)*
Note: * Only write 0 to clear the flag.
TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode.
The following describes bit 4. For details of the other bits in this register, see Section 15.2.2,
Timer Control/Status Register (TCSR).
The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized
in software standby mode.
Bit 4—Prescaler select (PSS): This bit selects the clock source input to WDT1 TCNT.
It also controls operation when shifting low power dissipation modes. The operating mode
selected after the SLEEP instruction is executed is determined in combination with other control
bits.
For details, see the description for clock selection in Section 15.2.2, Timer Control/Status Register
(TCSR), and this section.
Bit 4
PSS
Description
•
0
TCNT counts the divided clock from the ø -based prescaler (PSM).
•
When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode or software standby mode.
•
1
TCNT counts the divided clock from the øsubclock-based prescaler (PSS).
•
When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode, watch mode*, or sub-active mode*.
•
When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-
sleep mode, watch mode, or high-speed mode.
Note: * Always set high-speed mode when shifting to watch mode or sub-active mode.
864
7
6
OVF
WT/IT
0
0
R/W
5
4
TME
PSS
RST/NMI
0
0
R/W
R/W
3
2
CKS2
0
0
R/W
R/W
1
0
CKS1
CKS0
0
0
R/W
R/W
(Initial value)
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