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The timer output can be freely controlled by these compare match signals and the settings of bits
OS1 and OS0 of TCSR.
TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode.
13.2.3
Time Constant Registers B0 to B3 (TCORB0 to TCORB3)
Bit
:
15
Initial value
:
1
R/W
:
R/W
TCORB0 to TCORB3 are 8-bit readable/writable registers. TCORB0 and TCORB1 (TCORB2
and TCORB3) comprise a single 16-bit register so they can be accessed together by word transfer
instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag of TCSR is set. Note, however, that comparison is disabled during the
T2 state of a TCOR write cycle.
The timer output can be freely controlled by these compare match signals and the settings of
output select bits OS3 and OS2 of TCSR.
TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode.
13.2.4
Timer Control Registers 0 to 3 (TCR0 to TCR3)
Bit
:
CMIEB
Initial value
:
R/W
R/W
:
TCR0 to TCR3 are 8-bit readable/writable registers that select the input clock source and the time
at which TCNT is cleared, and enable interrupts.
TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode.
For details of this timing, see section 13.3, Operation.
526
TCORB0 (TCORB2)
14
13
12
11
1
1
1
1
R/W
R/W
R/W
R/W
7
6
CMIEA
OVIE
0
0
R/W
10
9
8
7
1
1
1
1
R/W
R/W
R/W
R/W
5
4
CCLR1
CCLR0
0
0
R/W
R/W
TCORB1 (TCORB3)
6
5
4
1
1
1
R/W
R/W
R/W
R/W
3
2
CKS2
CKS1
0
0
R/W
R/W
3
2
1
0
1
1
1
1
R/W
R/W
R/W
1
0
CKS0
0
0
R/W
R/W
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