Hitachi H8S/2645 Manuals

Manuals and User Guides for Hitachi H8S/2645. We have 1 Hitachi H8S/2645 manual available for free PDF download: Hardware Manual

Hitachi H8S/2645 Hardware Manual (1153 pages)

Hitachi 16-Bit Single-Chip Microcomputer H8S/2646 Series

Brand: Hitachi | Category: Desktop | Size: 3.74 MB

- 17
  Table of Contents
33
Overview
- 33
  Section 1 Overview
38
1.1Overview
- 38
  Internal Block Diagram
- 40
  Pin Description
  - 40
    Pin Arrangement
  - 42
    Pin Functions in Each Operating Mode
  - 52
    Pin Functions
  - 59
    Section 2 CPU
59
Cpu
- 60
  Differences Between H8S/2600 CPU and H8S/2000 CPU
- 61
  Differences From H8/300 CPU
- 61
  Differences From H8/300H CPU
- 59
  Overview
  - 59
    Features
- 62
  CPU Operating Modes
- 67
  Address Space
- 68
  Register Configuration
  - 68
    Overview
  - 69
    General Registers
  - 70
    Control Registers
  - 72
    Initial Register Values
- 73
  Data Formats
  - 73
    General Register Data Formats
  - 75
    Memory Data Formats
- 76
  Instruction Set
- 90
  Addressing Modes and Effective Address Calculation
  - 90
    Addressing Mode
  - 93
    Effective Address Calculation
- 97
  Processing States
  - 97
    Overview
  - 98
    Reset State
  - 99
    Exception-Handling State
  - 102
    Program Execution State
  - 102
    Bus-Released State
  - 102
    Power-Down State
- 103
  Basic Timing
  - 103
    Overview
  - 103
    On-Chip Memory (ROM, RAM)
  - 105
    On-Chip Supporting Module Access Timing
  - 107
    On-Chip HCAN Module Access Timing
  - 108
    External Address Space Access Timing
- 108
  Usage Note
111
MCU Operating Modes
- 112
  Register Configuration
- 111
  Overview
  - 111
    Operating Mode Selection
- 112
  Register Descriptions
- 116
  Operating Mode Descriptions
  - 116
    Mode 4
  - 116
    Mode 5
  - 116
    Mode 6
  - 116
    Mode 7
- 117
  Address Map in Each Operating Mode
- 117
  Pin Functions in Each Operating Mode
121
Exception Handling
- 122
  Exception Handling Operation
- 122
  Exception Vector Table
- 121
  Overview
  - 121
    Exception Handling Types and Priority
- 121
  Section 4 Exception Handling
- 124
  Reset
  - 124
    Overview
  - 124
    Reset Sequence
  - 126
    Interrupts After Reset
  - 127
    State of On-Chip Supporting Modules After Reset Release
- 127
  Traces
- 128
  Interrupts
- 129
  Trap Instruction
- 130
  Stack Status After Exception Handling
- 131
  Notes On Use of the Stack
133
Interrupt Controller
- 134
  Block Diagram
- 135
  Pin Configuration
- 135
  Register Configuration
- 133
  Overview
  - 133
    Features
- 133
  Section 5 Interrupt Controller
- 136
  Register Descriptions
- 141
  Interrupt Sources
  - 141
    External Interrupts
  - 142
    Internal Interrupts
  - 142
    Interrupt Exception Handling Vector Table
- 146
  Interrupt Operation
  - 146
    Interrupt Control Modes and Interrupt Operation
  - 149
    Interrupt Control Mode 0
  - 151
    Interrupt Control Mode 2
  - 153
    Interrupt Exception Handling Sequence
  - 154
    Interrupt Response Times
- 155
  Usage Notes
- 157
  DTC Activation By Interrupt
  - 157
    Overview
  - 157
    Block Diagram
  - 158
    Operation
- 161
  Overview
  - 161
    Features
  - 162
    Block Diagram
  - 163
    Register Configuration
161
PC Break Controller (PBC)
- 163
  Register Descriptions
- 167
  Operation
173
Bus Controller
- 174
  Block Diagram
- 175
  Pin Configuration
- 175
  Register Configuration
- 173
  Overview
  - 173
    Features
- 176
  Register Descriptions
- 186
  Overview of Bus Control
  - 186
    Area Partitioning
  - 187
    Bus Specifications
  - 188
    Memory Interfaces
  - 189
    Interface Specifications for Each Area
- 190
  Basic Bus Interface
  - 190
    Overview
  - 190
    Data Size and Data Alignment
  - 192
    Valid Strobes
  - 193
    Basic Timing
  - 201
    Wait Control
- 203
  Burst ROM Interface
  - 203
    Overview
  - 203
    Basic Timing
  - 205
    Wait Control
- 206
  Idle Cycle
  - 206
    Operation
  - 209
    Pin States During Idle Cycles
- 210
  Write Data Buffer Function
- 211
  Bus Arbitration
  - 211
    Overview
  - 211
    Operation
  - 211
    Bus Transfer Timing
- 212
  Resets and the Bus Controller
213
Data Transfer Controller (DTC)
- 213
  Overview
  - 213
    Features
  - 214
    Block Diagram
  - 215
    Register Configuration
- 216
  Register Descriptions
  - 216
    DTC Mode Register a (MRA)
  - 218
    DTC Mode Register B (MRB)
  - 219
    DTC Source Address Register (SAR)
  - 219
    DTC Destination Address Register (DAR)
  - 219
    DTC Transfer Count Register a (CRA)
  - 220
    DTC Transfer Count Register B (CRB)
  - 220
    DTC Enable Registers (DTCER)
  - 221
    DTC Vector Register (DTVECR)
  - 222
    Module Stop Control Register a (MSTPCRA)
- 224
  Operation
  - 224
    Overview
  - 226
    Activation Sources
  - 227
    DTC Vector Table
  - 231
    Location of Register Information in Address Space
  - 232
    Normal Mode
  - 233
    Repeat Mode
  - 234
    Block Transfer Mode
  - 236
    Chain Transfer
  - 237
    Operation Timing
  - 238
    Number of DTC Execution States
  - 240
    Procedures for Using DTC
  - 241
    Examples of Use of the DTC
- 244
  Interrupts
- 244
  Usage Notes
245
I/O Ports
- 245
  Overview
- 245
  Section 9 I/O Ports
- 253
  Port 1
  - 253
    Overview
  - 254
    Register Configuration
  - 256
    Pin Functions
- 264
  Port2
  - 264
    Overview
  - 264
    Register Configuration
  - 266
    Pin Functions
- 274
  Port3
  - 274
    Overview
  - 274
    Register Configuration
  - 277
    Pin Functions
- 279
  Port 4
  - 279
    Overview
  - 280
    Register Configuration
  - 280
    Pin Functions
- 281
  Port 5
  - 281
    Overview
  - 282
    Register Configuration
  - 283
    Pin Functions
- 285
  Port 9
  - 285
    Overview
  - 286
    Register Configuration
  - 286
    Pin Functions
- 287
  Port a
  - 287
    Overview
  - 288
    Register Configuration
  - 290
    Pin Functions
  - 292
    MOS Input Pull-Up Function
- 293
  Port B
  - 293
    Overview
  - 294
    Register Configuration
  - 296
    Pin Functions
  - 297
    MOS Input Pull-Up Function
- 298
  Port C
  - 298
    Overview
  - 299
    Register Configuration
  - 301
    Pin Functions
  - 302
    MOS Input Pull-Up Function
- 303
  Port D
  - 303
    Overview
  - 304
    Register Configuration
  - 306
    Pin Functions
  - 307
    MOS Input Pull-Up Function
- 308
  Port E
  - 308
    Overview
  - 309
    Register Configuration
  - 311
    Pin Functions
  - 311
    MOS Input Pull-Up Function
- 313
  Port F
  - 313
    Overview
  - 314
    Register Configuration
  - 316
    Pin Functions
- 319
  Port H
  - 319
    Overview
  - 319
    Register Configuration
  - 321
    Pin Functions
- 321
  Port J
  - 321
    Overview
  - 322
    Register Configuration
  - 323
    Pin Functions
- 324
  Port K
  - 324
    Overview
  - 324
    Register Configuration
  - 326
    Pin Functions
- 327
  Overview
  - 327
    Features
  - 331
    Block Diagram
  - 332
    Pin Configuration
  - 334
    Register Configuration
327
Section 10 16-Bit Timer Pulse Unit (TPU)
- 336
  Register Descriptions
  - 336
    Timer Control Register (TCR)
  - 341
    Timer Mode Register (TMDR)
  - 343
    Timer I/O Control Register (TIOR)
  - 356
    Timer Interrupt Enable Register (TIER)
  - 359
    Timer Status Register (TSR)
  - 363
    Timer Counter (TCNT)
  - 364
    Timer General Register (TGR)
  - 365
    Timer Start Register (TSTR)
  - 366
    Timer Synchro Register (TSYR)
  - 367
    Module Stop Control Register a (MSTPCRA)
- 368
  Interface to Bus Master
  - 368
    16-Bit Registers
- 370
  Operation
  - 370
    Overview
  - 371
    Basic Functions
  - 377
    Synchronous Operation
  - 379
    Buffer Operation
  - 383
    Cascaded Operation
  - 385
    PWM Modes
  - 390
    Phase Counting Mode
- 397
  Interrupts
  - 397
    Interrupt Sources and Priorities
  - 399
    DTC Activation
  - 399
    A/D Converter Activation
- 400
  Operation Timing
  - 400
    Input/Output Timing
  - 404
    Interrupt Signal Timing
- 408
  Usage Notes
- 419
  Overview
  - 419
    Features
  - 420
    Block Diagram
  - 421
    Pin Configuration
  - 422
    Registers
419
Section 11 Programmable Pulse Generator (PPG)
- 423
  Register Descriptions
- 433
  Operation
  - 433
    Overview
  - 434
    Output Timing
  - 435
    Normal Pulse Output
  - 437
    Non-Overlapping Pulse Output
  - 440
    Inverted Pulse Output
  - 441
    Pulse Output Triggered By Input Capture
- 442
  Usage Notes
- 445
  Overview
  - 445
    Features
  - 446
    Block Diagram
  - 448
    Pin Configuration
  - 448
    Register Configuration
445
Section 12 Watchdog Timer
- 449
  Register Descriptions
  - 449
    Timer Counter (TCNT)
  - 449
    Timer Control/Status Register (TCSR)
  - 454
    Reset Control/Status Register (RSTCSR)
  - 455
    Notes On Register Access
- 457
  Operation
- 461
  Interrupts
- 461
  Usage Notes
- 463
  Overview
  - 463
    Features
  - 465
    Block Diagram
  - 466
    Pin Configuration
  - 467
    Register Configuration
463
Section 13 Serial Communication Interface (SCI)
- 468
  Register Descriptions
  - 468
    Receive Shift Register (RSR)
  - 468
    Receive Data Register (RDR)
  - 469
    Transmit Shift Register (TSR)
  - 469
    Transmit Data Register (TDR)
  - 470
    Serial Mode Register (SMR)
  - 473
    Serial Control Register (SCR)
  - 477
    Serial Status Register (SSR)
  - 481
    Bit Rate Register (BRR)
  - 488
    Smart Card Mode Register (SCMR)
  - 489
    Module Stop Control Register B (MSTPCRB)
- 491
  Operation
  - 491
    Overview
  - 493
    Operation in Asynchronous Mode
  - 504
    Multiprocessor Communication Function
  - 512
    Operation in Clocked Synchronous Mode
- 520
  SCI Interrupts
- 521
  Usage Notes
- 531
  Overview
  - 531
    Features
  - 532
    Block Diagram
  - 533
    Pin Configuration
  - 534
    Register Configuration
531
Section 14 Smart Card Interface
- 535
  Register Descriptions
  - 535
    Smart Card Mode Register (SCMR)
  - 537
    Serial Status Register (SSR)
  - 539
    Serial Mode Register (SMR)
  - 541
    Serial Control Register (SCR)
- 542
  Operation
  - 542
    Overview
  - 542
    Pin Connections
  - 544
    Data Format
  - 546
    Register Settings
  - 548
    Clock
  - 550
    Data Transfer Operations
  - 557
    Operation in GSM Mode
  - 558
    Operation in Block Transfer Mode
- 559
  Usage Notes
- 563
  Overview
  - 563
    Features
  - 564
    Block Diagram
  - 565
    Pin Configuration
  - 565
    Register Configuration
563
Section 15 Hitachi Controller Area Network (HCAN)
- 567
  Register Descriptions
  - 567
    Master Control Register (MCR)
  - 568
    General Status Register (GSR)
  - 570
    Bit Configuration Register (BCR)
  - 572
    Mailbox Configuration Register (MBCR)
  - 573
    Transmit Wait Register (TXPR)
  - 574
    Transmit Wait Cancel Register (TXCR)
  - 575
    Transmit Acknowledge Register (TXACK)
  - 576
    Abort Acknowledge Register (ABACK)
  - 577
    Receive Complete Register (RXPR)
  - 578
    Remote Request Register (RFPR)
  - 579
    Interrupt Register (IRR)
  - 583
    Mailbox Interrupt Mask Register (MBIMR)
  - 584
    Interrupt Mask Register (IMR)
  - 586
    Receive Error Counter (REC)
  - 586
    Transmit Error Counter (TEC)
  - 587
    Unread Message Status Register (UMSR)
  - 588
    Local Acceptance Filter Masks (LAFML, LAFMH)
  - 589
    Message Control (MC0 to MC15)
  - 593
    Message Data (MD0 to MD15)
  - 593
    Module Stop Control Register C (MSTPCRC)
- 594
  Operation
  - 594
    Hardware and Software Resets
  - 594
    Initialization After Hardware Reset
  - 601
    Transmit Mode
  - 607
    Receive Mode
  - 613
    HCAN Sleep Mode
  - 614
    HCAN Halt Mode
  - 615
    Interrupt Interface
  - 616
    DTC Interface
- 617
  CAN Bus Interface
- 617
  Usage Notes
- 619
  Overview
  - 619
    Features
  - 620
    Block Diagram
  - 621
    Pin Configuration
  - 622
    Register Configuration
619
Section 16 A/D Converter
- 623
  Register Descriptions
- 629
  Interface to Bus Master
- 630
  Operation
  - 630
    Single Mode (SCAN = 0)
  - 632
    Scan Mode (SCAN = 1)
  - 634
    Input Sampling and A/D Conversion Time
  - 635
    External Trigger Input Timing
- 636
  Interrupts
- 636
  Usage Notes
- 643
  Overview
  - 643
    Features
  - 644
    Block Diagram
  - 646
    Pin Configuration
  - 647
    Register Configuration
643
Section 17 Motor Control PWM Timer
- 648
  Register Descriptions
- 658
  Bus Master Interface
  - 658
    16-Bit Data Registers
- 659
  Operation
  - 659
    PWM Channel 1 Operation
  - 660
    PWM Channel 2 Operation
- 661
  Usage Note
- 663
  Overview
  - 663
    Features
  - 664
    Block Diagram
  - 665
    Pin Configuration
  - 665
    Register Configuration
663
Section 18 LCD Controller/Driver
- 666
  Register Descriptions
- 673
  Operation
- 685
  Overview
  - 685
    Block Diagram
  - 686
    Register Configuration
685
Section 19 RAM
- 686
  Register Descriptions
  - 686
    System Control Register (SYSCR)
- 687
  Operation
- 687
  Usage Notes
- 689
  Features
689
Section 20 ROM
- 690
  Overview
  - 690
    Block Diagram
  - 691
    Mode Transitions
  - 692
    On-Board Programming Modes
  - 694
    Flash Memory Emulation in RAM
  - 695
    Differences Between Boot Mode and User Program Mode
  - 696
    Block Configuration
- 697
  Pin Configuration
- 698
  Register Configuration
- 698
  Register Descriptions
- 705
  On-Board Programming Modes
  - 705
    Boot Mode
  - 710
    User Program Mode
- 712
  Flash Memory Programming/Erasing
  - 714
    Program Mode
  - 715
    Program-Verify Mode
  - 719
    Erase Mode
  - 719
    Erase-Verify Mode
- 721
  Protection
  - 721
    Hardware Protection
  - 722
    Software Protection
  - 723
    Error Protection
- 725
  Flash Memory Emulation in RAM
- 727
  Flash Memory Programmer Mode
  - 728
    20.11.1 Socket Adapter Pin Correspondence Diagram
  - 730
    20.11.2 Programmer Mode Operation
  - 731
    20.11.3 Memory Read Mode
  - 734
    20.11.4 Auto-Program Mode
  - 736
    20.11.5 Auto-Erase Mode
  - 738
    20.11.6 Status Read Mode
  - 739
    20.11.7 Status Polling
  - 739
    20.11.8 Programmer Mode Transition Time
  - 740
    20.11.9 Notes On Memory Programming
- 727
  Interrupt Handling When Programming/Erasing Flash Memory
- 741
  Flash Memory and Power-Down States
  - 741
    20.12.1 Notes On Power-Down States
- 742
  Flash Memory Programming and Erasing Precautions
- 747
  Overview
  - 747
    Block Diagram
  - 748
    Register Configuration
747
Section 21 Clock Pulse Generator
- 748
  Register Descriptions
  - 748
    System Clock Control Register (SCKCR)
  - 749
    Low-Power Control Register (LPWRCR)
- 750
  Oscillator
  - 750
    Connecting a Crystal Resonator
- 753
  Bus Master Clock Selection Circuit
- 753
  Medium-Speed Clock Divider
- 753
  PLL Circuit
- 754
  Subclock Oscillator
- 755
  Note On Crystal Resonator
- 755
  Subclock Waveform Generation Circuit
- 757
  Overview
  - 761
    Register Configuration
757
Section 22 Power-Down Modes
- 762
  Register Descriptions
- 770
  Medium-Speed Mode
- 771
  Sleep Mode
  - 771
    Exiting Sleep Mode
- 772
  Module Stop Mode
  - 773
    Usage Notes
- 774
  Software Standby Mode
- 777
  Hardware Standby Mode
  - 778
    Hardware Standby Mode Timing
- 778
  Watch Mode
  - 779
    Exiting Watch Mode
  - 779
    Notes
- 780
  Sub-Sleep Mode
  - 780
    Exiting Sub-Sleep Mode
- 781
  Sub-Active Mode
  - 781
    22.10.2 Exiting Sub-Active Mode
- 782
  Clock Output Disabling Function
- 782
  Direct Transitions
  - 782
    22.11.1 Overview of Direct Transitions
- 783
  Usage Notes
- 785
  Absolute Maximum Ratings
785
Section 23 Electrical Characteristics
- 786
  Power Supply Voltage and Operating Frequency Range
- 787
  DC Characteristics
- 792
  AC Characteristics
  - 793
    Clock Timing
  - 795
    Control Signal Timing
  - 797
    Bus Timing
  - 803
    Timing of On-Chip Supporting Modules
- 808
  A/D Conversion Characteristics
- 809
  LCD Characteristics
- 810
  Flash Memory Characteristics
813
Appendix A Instruction Set
- 813
  Instruction List
- 837
  A.2 Instruction Codes
- 837
  Instruction Codes
- 852
  Operation Code Map
- 856
  Number of States Required for Instruction Execution
- 870
  Bus States During Instruction Execution
- 884
  Condition Code Modification
- 890
  Address
890
Appendix B Internal I/O Register
- 906
  B.2 Functions
- 906
  Functions
1107
Appendix C I/O Port Block Diagrams
- 1113
  C.2 Port 2 Block Diagrams
- 1113
  Port 2 Block Diagrams
- 1115
  C.3 Port 3 Block Diagrams
- 1115
  Port 3 Block Diagrams
- 1122
  C.4 Port 4 Block Diagram
- 1122
  Port 4 Block Diagram
- 1123
  C.5 Port 5 Block Diagrams
- 1123
  Port 5 Block Diagrams
- 1127
  C.6 Port 9 Block Diagram
- 1127
  Port 9 Block Diagram
- 1128
  C.7 Port a Block Diagram
- 1128
  Port a Block Diagram
- 1129
  C.8 Port B Block Diagram
- 1129
  Port B Block Diagram
- 1130
  C.9 Port C Block Diagram
- 1130
  Port C Block Diagram
- 1131
  C.10 Port D Block Diagram
- 1131
  Port D Block Diagram
- 1132
  C.11 Port E Block Diagram
- 1132
  Port E Block Diagram
- 1133
  C.12 Port F Block Diagrams
- 1133
  Port F Block Diagrams
- 1140
  C.13 Port G Block Diagram
- 1140
  Port G Block Diagram
- 1141
  C.14 Port J Block Diagram
- 1141
  Port J Block Diagram
- 1142
  C.15 Port K Block Diagram
- 1142
  Port K Block Diagram
1143
Appendix D Pin States
1150
Appendix E Timing of Transition to and Recovery
1150
Appendix F Package Dimensions

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Hitachi H8S/2645 Manuals

Manuals and User Guides for Hitachi H8S/2645. We have 1 Hitachi H8S/2645 manual available for free PDF download: Hardware Manual

Hitachi H8S/2645 Hardware Manual (1153 pages)

Table of Contents

33 Overview

38 1.1Overview

59 Cpu

111 MCU Operating Modes

121 Exception Handling

133 Interrupt Controller

161 PC Break Controller (PBC)

173 Bus Controller

213 Data Transfer Controller (DTC)

245 I/O Ports

327 Section 10 16-Bit Timer Pulse Unit (TPU)

419 Section 11 Programmable Pulse Generator (PPG)

445 Section 12 Watchdog Timer

463 Section 13 Serial Communication Interface (SCI)

531 Section 14 Smart Card Interface

563 Section 15 Hitachi Controller Area Network (HCAN)

619 Section 16 A/D Converter

643 Section 17 Motor Control PWM Timer

663 Section 18 LCD Controller/Driver

685 Section 19 RAM

689 Section 20 ROM

747 Section 21 Clock Pulse Generator

757 Section 22 Power-Down Modes

785 Section 23 Electrical Characteristics

813 Appendix A Instruction Set

890 Appendix B Internal I/O Register

1107 Appendix C I/O Port Block Diagrams

1143 Appendix D Pin States

1150 Appendix E Timing of Transition to and Recovery

1150 Appendix F Package Dimensions

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Hitachi Categories

33
Overview

38
1.1Overview

59
Cpu

111
MCU Operating Modes

121
Exception Handling

133
Interrupt Controller

161
PC Break Controller (PBC)

173
Bus Controller

213
Data Transfer Controller (DTC)

245
I/O Ports

327
Section 10 16-Bit Timer Pulse Unit (TPU)

419
Section 11 Programmable Pulse Generator (PPG)

445
Section 12 Watchdog Timer

463
Section 13 Serial Communication Interface (SCI)

531
Section 14 Smart Card Interface

563
Section 15 Hitachi Controller Area Network (HCAN)

619
Section 16 A/D Converter

643
Section 17 Motor Control PWM Timer

663
Section 18 LCD Controller/Driver

685
Section 19 RAM

689
Section 20 ROM

747
Section 21 Clock Pulse Generator

757
Section 22 Power-Down Modes

785
Section 23 Electrical Characteristics

813
Appendix A Instruction Set

890
Appendix B Internal I/O Register

1107
Appendix C I/O Port Block Diagrams

1143
Appendix D Pin States

1150
Appendix E Timing of Transition to and Recovery

1150
Appendix F Package Dimensions