Hitachi H8S/2645 Manuals

Manuals and User Guides for Hitachi H8S/2645. We have 1 Hitachi H8S/2645 manual available for free PDF download: Hardware Manual

Hitachi H8S/2645 Hardware Manual (1153 pages)

Hitachi 16-Bit Single-Chip Microcomputer H8S/2646 Series

Brand: Hitachi | Category: Desktop | Size: 3.74 MB

Table Of Contents17................................................................................................................................................................

Section 1 Overview33................................................................................................................................................................

Internal Block Diagram38................................................................................................................................................................

Pin Description40................................................................................................................................................................

Pin Functions In Each Operating Mode42................................................................................................................................................................

Pin Functions52................................................................................................................................................................

Section 2 Cpu59................................................................................................................................................................

Differences Between H8s/2600 Cpu And H8s/2000 Cpu60................................................................................................................................................................

Differences From H8/300 Cpu61................................................................................................................................................................

Cpu Operating Modes62................................................................................................................................................................

Address Space67................................................................................................................................................................

Register Configuration68................................................................................................................................................................

General Registers69................................................................................................................................................................

Control Registers70................................................................................................................................................................

Initial Register Values72................................................................................................................................................................

Data Formats73................................................................................................................................................................

Memory Data Formats75................................................................................................................................................................

Instruction Set76................................................................................................................................................................

Instructions And Addressing Modes77................................................................................................................................................................

Table Of Instructions Classified By Function79................................................................................................................................................................

Basic Instruction Formats88................................................................................................................................................................

Addressing Modes And Effective Address Calculation90................................................................................................................................................................

Effective Address Calculation93................................................................................................................................................................

Processing States97................................................................................................................................................................

Reset State98................................................................................................................................................................

Exception-handling State99................................................................................................................................................................

Program Execution State102................................................................................................................................................................

Basic Timing103................................................................................................................................................................

On-chip Supporting Module Access Timing105................................................................................................................................................................

On-chip Hcan Module Access Timing107................................................................................................................................................................

External Address Space Access Timing108................................................................................................................................................................

Section 3 Mcu Operating Modes111................................................................................................................................................................

System Control Register (syscr)113................................................................................................................................................................

Pin Function Control Register (pfcr)114................................................................................................................................................................

Operating Mode Descriptions116................................................................................................................................................................

Section 4 Exception Handling121................................................................................................................................................................

Exception Handling Operation122................................................................................................................................................................

Reset124................................................................................................................................................................

Interrupts After Reset126................................................................................................................................................................

State Of On-chip Supporting Modules After Reset Release127................................................................................................................................................................

Interrupts128................................................................................................................................................................

Trap Instruction129................................................................................................................................................................

Stack Status After Exception Handling130................................................................................................................................................................

Notes On Use Of The Stack131................................................................................................................................................................

Section 5 Interrupt Controller133................................................................................................................................................................

Block Diagram134................................................................................................................................................................

Pin Configuration135................................................................................................................................................................

Register Descriptions136................................................................................................................................................................

Irq Enable Register (ier)138................................................................................................................................................................

Irq Sense Control Registers H And L (iscrh, Iscrl)139................................................................................................................................................................

Irq Status Register (isr)140................................................................................................................................................................

Interrupt Sources141................................................................................................................................................................

Internal Interrupts142................................................................................................................................................................

Interrupt Operation146................................................................................................................................................................

Interrupt Control Mode 0149................................................................................................................................................................

Interrupt Control Mode 2151................................................................................................................................................................

Interrupt Exception Handling Sequence153................................................................................................................................................................

Interrupt Response Times154................................................................................................................................................................

Usage Notes155................................................................................................................................................................

Instructions That Disable Interrupts156................................................................................................................................................................

Interrupts During Execution Of Eepmov Instruction157................................................................................................................................................................

Operation158................................................................................................................................................................

Section 6 Pc Break Controller (pbc)161................................................................................................................................................................

Break Address Register B (barb)164................................................................................................................................................................

Break Control Register B (bcrb)166................................................................................................................................................................

Notes On Pc Break Interrupt Handling168................................................................................................................................................................

Pc Break Operation In Continuous Data Transfer169................................................................................................................................................................

When Instruction Execution Is Delayed By One State170................................................................................................................................................................

Additional Notes171................................................................................................................................................................

Section 7 Bus Controller173................................................................................................................................................................

Wait Control Registers H And L (wcrh, Wcrl)178................................................................................................................................................................

Bus Control Register H (bcrh)182................................................................................................................................................................

Bus Control Register L (bcrl)183................................................................................................................................................................

Overview Of Bus Control186................................................................................................................................................................

Bus Specifications187................................................................................................................................................................

Memory Interfaces188................................................................................................................................................................

Interface Specifications For Each Area189................................................................................................................................................................

Basic Bus Interface190................................................................................................................................................................

Valid Strobes192................................................................................................................................................................

Wait Control201................................................................................................................................................................

Burst Rom Interface203................................................................................................................................................................

Idle Cycle206................................................................................................................................................................

Pin States During Idle Cycles209................................................................................................................................................................

Write Data Buffer Function210................................................................................................................................................................

Bus Arbitration211................................................................................................................................................................

Resets And The Bus Controller212................................................................................................................................................................

Section 8 Data Transfer Controller (dtc)213................................................................................................................................................................

Dtc Mode Register B (mrb)218................................................................................................................................................................

Dtc Source Address Register (sar)219................................................................................................................................................................

Dtc Transfer Count Register B (crb)220................................................................................................................................................................

Dtc Vector Register (dtvecr)221................................................................................................................................................................

Module Stop Control Register A (mstpcra)222................................................................................................................................................................

Activation Sources226................................................................................................................................................................

Dtc Vector Table227................................................................................................................................................................

Location Of Register Information In Address Space231................................................................................................................................................................

Normal Mode232................................................................................................................................................................

Repeat Mode233................................................................................................................................................................

Block Transfer Mode234................................................................................................................................................................

Chain Transfer236................................................................................................................................................................

Operation Timing237................................................................................................................................................................

Number Of Dtc Execution States238................................................................................................................................................................

Procedures For Using Dtc240................................................................................................................................................................

Examples Of Use Of The Dtc241................................................................................................................................................................

Section 9 I/o Ports245................................................................................................................................................................

Port253................................................................................................................................................................

Overview287................................................................................................................................................................

Mos Input Pull-up Function292................................................................................................................................................................

Section 10 16-bit Timer Pulse Unit (tpu)327................................................................................................................................................................

Timer Mode Register (tmdr)341................................................................................................................................................................

Timer I/o Control Register (tior)343................................................................................................................................................................

Timer Interrupt Enable Register (tier)356................................................................................................................................................................

Timer Status Register (tsr)359................................................................................................................................................................

Timer Counter (tcnt)363................................................................................................................................................................

Timer General Register (tgr)364................................................................................................................................................................

Timer Start Register (tstr)365................................................................................................................................................................

Timer Synchro Register (tsyr)366................................................................................................................................................................

Interface To Bus Master368................................................................................................................................................................

Basic Functions371................................................................................................................................................................

Synchronous Operation377................................................................................................................................................................

Buffer Operation379................................................................................................................................................................

Cascaded Operation383................................................................................................................................................................

Pwm Modes385................................................................................................................................................................

Phase Counting Mode390................................................................................................................................................................

Dtc Activation399................................................................................................................................................................

Interrupt Signal Timing404................................................................................................................................................................

Section 11 Programmable Pulse Generator (ppg)419................................................................................................................................................................

Registers422................................................................................................................................................................

Output Data Registers H And L (podrh, Podrl)424................................................................................................................................................................

Next Data Registers H And L (ndrh, Ndrl)425................................................................................................................................................................

Ppg Output Control Register (pcr)427................................................................................................................................................................

Ppg Output Mode Register (pmr)429................................................................................................................................................................

Port 1 Data Direction Register (p1ddr)432................................................................................................................................................................

Output Timing434................................................................................................................................................................

Normal Pulse Output435................................................................................................................................................................

Non-overlapping Pulse Output437................................................................................................................................................................

Inverted Pulse Output440................................................................................................................................................................

Pulse Output Triggered By Input Capture441................................................................................................................................................................

Section 12 Watchdog Timer445................................................................................................................................................................

Reset Control/status Register (rstcsr)454................................................................................................................................................................

Notes On Register Access455................................................................................................................................................................

Interval Timer Operation459................................................................................................................................................................

Timing Of Setting Of Watchdog Timer Overflow Flag (wovf)460................................................................................................................................................................

Changing Value Of Pss And Cks2 To Cks0462................................................................................................................................................................

Section 13 Serial Communication Interface (sci)463................................................................................................................................................................

Transmit Shift Register (tsr)469................................................................................................................................................................

Serial Mode Register (smr)470................................................................................................................................................................

Serial Control Register (scr)473................................................................................................................................................................

Serial Status Register (ssr)477................................................................................................................................................................

Bit Rate Register (brr)481................................................................................................................................................................

Smart Card Mode Register (scmr)488................................................................................................................................................................

Module Stop Control Register B (mstpcrb)489................................................................................................................................................................

Operation In Asynchronous Mode493................................................................................................................................................................

Multiprocessor Communication Function504................................................................................................................................................................

Operation In Clocked Synchronous Mode512................................................................................................................................................................

Sci Interrupts520................................................................................................................................................................

Section 14 Smart Card Interface531................................................................................................................................................................

Data Format544................................................................................................................................................................

Register Settings546................................................................................................................................................................

Clock548................................................................................................................................................................

Data Transfer Operations550................................................................................................................................................................

Operation In Gsm Mode557................................................................................................................................................................

Operation In Block Transfer Mode558................................................................................................................................................................

Section 15 Hitachi Controller Area Network (hcan)563................................................................................................................................................................

General Status Register (gsr)568................................................................................................................................................................

Bit Configuration Register (bcr)570................................................................................................................................................................

Mailbox Configuration Register (mbcr)572................................................................................................................................................................

Transmit Wait Register (txpr)573................................................................................................................................................................

Transmit Wait Cancel Register (txcr)574................................................................................................................................................................

Transmit Acknowledge Register (txack)575................................................................................................................................................................

Abort Acknowledge Register (aback)576................................................................................................................................................................

Receive Complete Register (rxpr)577................................................................................................................................................................

Remote Request Register (rfpr)578................................................................................................................................................................

Interrupt Register (irr)579................................................................................................................................................................

Mailbox Interrupt Mask Register (mbimr)583................................................................................................................................................................

Interrupt Mask Register (imr)584................................................................................................................................................................

Receive Error Counter (rec)586................................................................................................................................................................

Unread Message Status Register (umsr)587................................................................................................................................................................

Local Acceptance Filter Masks (lafml, Lafmh)588................................................................................................................................................................

Message Control (mc0 To Mc15)589................................................................................................................................................................

Message Data (md0 To Md15)593................................................................................................................................................................

Transmit Mode601................................................................................................................................................................

Receive Mode607................................................................................................................................................................

Hcan Sleep Mode613................................................................................................................................................................

Hcan Halt Mode614................................................................................................................................................................

Interrupt Interface615................................................................................................................................................................

Dtc Interface616................................................................................................................................................................

Can Bus Interface617................................................................................................................................................................

Section 16 A/d Converter619................................................................................................................................................................

A/d Control/status Register (adcsr)624................................................................................................................................................................

A/d Control Register (adcr)627................................................................................................................................................................

Scan Mode (scan = 1)632................................................................................................................................................................

Input Sampling And A/d Conversion Time634................................................................................................................................................................

External Trigger Input Timing635................................................................................................................................................................

Section 17 Motor Control Pwm Timer643................................................................................................................................................................

Pwm Output Control Registers 1 And 2 (pwocr1, Pwocr2)649................................................................................................................................................................

Pwm Polarity Registers 1 And 2 (pwpr1, Pwpr2)650................................................................................................................................................................

Pwm Counters 1 And 2 (pwcnt1, Pwcnt2)651................................................................................................................................................................

Pwm Duty Registers 1a, 1c, 1e, 1g (pwdtr1a, 1c, 1e, 1g)652................................................................................................................................................................

Pwm Buffer Registers 1a, 1c, 1e, 1g (pwbfr1a, 1c, 1e, 1g)654................................................................................................................................................................

Pwm Buffer Registers 2a To 2d (pwbfr2a To Pwbfr2d)656................................................................................................................................................................

Module Stop Control Register D (mstpcrd)657................................................................................................................................................................

Bus Master Interface658................................................................................................................................................................

Pwm Channel 2 Operation660................................................................................................................................................................

Usage Note661................................................................................................................................................................

Section 18 Lcd Controller/driver663................................................................................................................................................................

Lcd Control Register (lcr)669................................................................................................................................................................

Lcd Control Register 2 (lcr2)671................................................................................................................................................................

Relationship Between Lcd Ram And Display675................................................................................................................................................................

Operation In Power-down Modes683................................................................................................................................................................

Boosting The Lcd Drive Power Supply684................................................................................................................................................................

Section 19 Ram685................................................................................................................................................................

Section 20 Rom689................................................................................................................................................................

Mode Transitions691................................................................................................................................................................

Boot Mode692................................................................................................................................................................

Flash Memory Emulation In Ram694................................................................................................................................................................

Differences Between Boot Mode And User Program Mode695................................................................................................................................................................

Block Configuration696................................................................................................................................................................

Flash Memory Control Register 2 (flmcr2)701................................................................................................................................................................

Erase Block Register 1 (ebr1)702................................................................................................................................................................

Ram Emulation Register (ramer)703................................................................................................................................................................

Flash Memory Power Control Register (flpwcr)704................................................................................................................................................................

On-board Programming Modes705................................................................................................................................................................

User Program Mode710................................................................................................................................................................

Flash Memory Programming/erasing712................................................................................................................................................................

Program Mode714................................................................................................................................................................

Program-verify Mode715................................................................................................................................................................

Erase Mode719................................................................................................................................................................

Protection721................................................................................................................................................................

Software Protection722................................................................................................................................................................

Error Protection723................................................................................................................................................................

Interrupt Handling When Programming/erasing Flash Memory727................................................................................................................................................................

Socket Adapter Pin Correspondence Diagram728................................................................................................................................................................

Programmer Mode Operation730................................................................................................................................................................

Memory Read Mode731................................................................................................................................................................

Auto-program Mode734................................................................................................................................................................

Auto-erase Mode736................................................................................................................................................................

Status Read Mode738................................................................................................................................................................

Status Polling739................................................................................................................................................................

Notes On Memory Programming740................................................................................................................................................................

Flash Memory And Power-down States741................................................................................................................................................................

Flash Memory Programming And Erasing Precautions742................................................................................................................................................................

Section 21 Clock Pulse Generator747................................................................................................................................................................

Low-power Control Register (lpwrcr)749................................................................................................................................................................

Oscillator750................................................................................................................................................................

Pll Circuit753................................................................................................................................................................

Subclock Oscillator754................................................................................................................................................................

Subclock Waveform Generation Circuit755................................................................................................................................................................

Section 22 Power-down Modes757................................................................................................................................................................

System Clock Control Register (sckcr)764................................................................................................................................................................

Timer Control/status Register (tcsr)768................................................................................................................................................................

Module Stop Control Register (mstpcr)769................................................................................................................................................................

Medium-speed Mode770................................................................................................................................................................

Sleep Mode771................................................................................................................................................................

Module Stop Mode772................................................................................................................................................................

Software Standby Mode774................................................................................................................................................................

Setting Oscillation Stabilization Time After Clearing Software Standby Mode775................................................................................................................................................................

Hardware Standby Mode777................................................................................................................................................................

Hardware Standby Mode Timing778................................................................................................................................................................

Exiting Watch Mode779................................................................................................................................................................

Sub-sleep Mode780................................................................................................................................................................

Sub-active Mode781................................................................................................................................................................

Direct Transitions782................................................................................................................................................................

Section 23 Electrical Characteristics785................................................................................................................................................................

Absolute Maximum Ratings785................................................................................................................................................................

Power Supply Voltage And Operating Frequency Range786................................................................................................................................................................

Dc Characteristics787................................................................................................................................................................

Ac Characteristics792................................................................................................................................................................

Clock Timing793................................................................................................................................................................

Control Signal Timing795................................................................................................................................................................

Bus Timing797................................................................................................................................................................

Timing Of On-chip Supporting Modules803................................................................................................................................................................

A/d Conversion Characteristics808................................................................................................................................................................

Lcd Characteristics809................................................................................................................................................................

Flash Memory Characteristics810................................................................................................................................................................

Appendix A Instruction Set813................................................................................................................................................................

A.2 Instruction Codes837................................................................................................................................................................

A.3 Operation Code Map852................................................................................................................................................................

A.4 Number Of States Required For Instruction Execution856................................................................................................................................................................

A.5 Bus States During Instruction Execution870................................................................................................................................................................

A.6 Condition Code Modification884................................................................................................................................................................

Appendix B Internal I/o Register890................................................................................................................................................................

B.2 Functions906................................................................................................................................................................

Appendix C I/o Port Block Diagrams1107................................................................................................................................................................

C.2 Port 2 Block Diagrams1113................................................................................................................................................................

C.3 Port 3 Block Diagrams1115................................................................................................................................................................

C.4 Port 4 Block Diagram1122................................................................................................................................................................

C.5 Port 5 Block Diagrams1123................................................................................................................................................................

C.6 Port 9 Block Diagram1127................................................................................................................................................................

C.7 Port A Block Diagram1128................................................................................................................................................................

C.8 Port B Block Diagram1129................................................................................................................................................................

C.9 Port C Block Diagram1130................................................................................................................................................................

C.10 Port D Block Diagram1131................................................................................................................................................................

C.11 Port E Block Diagram1132................................................................................................................................................................

C.12 Port F Block Diagrams1133................................................................................................................................................................

C.13 Port G Block Diagram1140................................................................................................................................................................

C.14 Port J Block Diagram1141................................................................................................................................................................

C.15 Port K Block Diagram1142................................................................................................................................................................

Appendix D Pin States1143................................................................................................................................................................

Appendix F Package Dimensions1150................................................................................................................................................................