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Hitachi H8S/2633 Hardware Manual page 724

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Bit 5
Bit 4
MST
TRS
0
0
1
1
0
1
Bit 5
MST
Description
0
Slave mode
[Clearing conditions]
1. When 0 is written by software
2. When bus arbitration is lost after transmission is started in I
format master mode
1
Master mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing condition 2)
2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2)
Bit 4
TRS
Description
0
Receive mode
[Clearing conditions]
1. When 0 is written by software (in cases other than setting condition
3)
2. When 0 is written in TRS after reading TRS = 1 (in case of clearing
condition 3)
3. When bus arbitration is lost after transmission is started in I
format master mode
4. When the SW bit in DDCSWR changes from 1 to 0
1
Transmit mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing conditions 3 and 4)
2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3
and 4)
3. When a 1 is received as the R/W bit of the first frame in I
706
Operating Mode
Slave receive mode
Slave transmit mode
Master receive mode
Master transmit mode
(Initial value)
(Initial value)
2
C bus
(Initial value)
2
C bus
2
C bus format slave mode

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