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Hitachi H8S/2633 Hardware Manual page 693

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17.3.4
Register Settings
Table 17-3 shows a bit map of the registers used by the smart card interface.
Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described
below.
Table 17-3 Smart Card Interface Register Settings
Register
Bit 7
SMR
GM
BRR
BRR7
SCR
TIE
TDR
TDR7
SSR
TDRE
RDR
RDR7
SCMR
Notes: — : Unused bit.
*: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.
SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in
GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1
if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. Bits BCP1 and
BCP0 select the number of basic clock periods in a 1-bit transfer interval. For details, see section
17.3.5, Clock.
The BLK bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer
mode.
BRR Setting: BRR is used to set the bit rate. See section 17.3.5, Clock, for the method of
calculating the value to be set.
SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.
For details, see section 16, Serial Communication Interface.
Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these
bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in
SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.
Bit 6
Bit 5
BLK
1
BRR6
BRR5
RIE
TE
TDR6
TDR5
RDRF
ORER
RDR6
RDR5
Bit
Bit 4
Bit 3
O/E
BCP1
BRR4
BRR3
RE
0
TDR4
TDR3
ERS
PER
RDR4
RDR3
SDIR
Bit 2
Bit 1
BCP0
CKS1
BRR2
BRR1
0
CKE1*
TDR2
TDR1
TEND
0
RDR2
RDR1
SINV
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF
675

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