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Name
Wait
Bus request
Bus request
acknowledge
Bus request output
7.1.4
Register Configuration
Table 7-2 summarizes the registers of the bus controller.
Table 7-2
Bus Controller Registers
Name
Bus width control register
Access state control register
Wait control register H
Wait control register L
Bus control register H
Bus control register L
Pin function control register
Memory control register
DRAM control register
Refresh timer counter
Refresh time constant register
Notes: 1. Lower 16 bits of the address.
2. Determined by the MCU operating mode.
Symbol
I/O
WAIT
Input
BREQ
Input
BACK
Output
BREQO
Output
Abbreviation
ABWCR
ASTCR
WCRH
WCRL
BCRH
BCRL
PFCR
MCR
DRAMCR
RTCNT
RTCOR
Function
Wait request signal when accessing external 3-state
access space.
Request signal that releases bus to external device.
Acknowledge signal indicating that bus has been
released.
External bus request signal used when internal bus
master accesses external space when external bus is
released.
Power-On
R/W
Reset
R/W
H'FF/H'00*
R/W
H'FF
R/W
H'FF
R/W
H'FF
R/W
H'D0
R/W
H'08
R/W
H'0D/H'00
R/W
H'00
R/W
H'00
R/W
H'00
R/W
H'FF
Initial Value
Manual
Reset
2
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
1
Address*
H'FED0
H'FED1
H'FED2
H'FED3
H'FED4
H'FED5
H'FDEB
H'FED6
H'FED7
H'FED8
H'FED9
135
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