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• Idle cycle insertion
An idle cycle can be inserted in case of an external read cycle between different areas
An idle cycle can be inserted in case of an external write cycle immediately after an
external read cycle
• Write buffer functions
External write cycle and internal access can be executed in parallel
DMAC single-address mode and internal access can be executed in parallel.
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC and DTC
• Other features
Refresh counter (refresh timer) can be used as an interval timer.
External bus release function
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