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16-Bit 2-State Access Space: Figures 7-8 to 7-10 show bus timings for a 16-bit 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address.
Wait states cannot be inserted.
Read
Write
Note: n = 0 to 7
Figure 7-8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
164
ø
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Bus cycle
T
T
1
2
High
Valid
High impedance
Valid
Invalid
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