Hitachi H8S/2633 Hardware Manual page 754

3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or

according to the ICE bit.

4. Initialize (re-set) the IIC registers.

• In master mode, if an instruction to generate a start condition is immediately followed by an

instruction to generate a stop condition, neither condition will be output correctly. To output

consecutive start and stop conditions, after issuing the instruction that generates the start

condition, read the relevant ports, check that SCL and SDA are both low, then issue the

instruction that generates the stop condition. Note that SCL may not yet have gone low when

BBSY is cleared to 0.

• Either of the following two conditions will start the next transfer. Pay attention to these

conditions when reading or writing to ICDR.

 Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from

ICDRT to ICDRS)

 Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from

ICDRS to ICDRR)

• Table 18-6 shows the timing of SCL and SDA output in synchronization with the internal

clock. Timings on the bus are determined by the rise and fall times of signals affected by the

bus load capacitance, series resistance, and parallel resistance.

Table 18-6 I

C Bus Timing (SCL and SDA Output)

SCL output cycle time

SCL output high pulse width

SCL output low pulse width

SDA output bus free time

Start condition output hold time

Retransmission start condition output

Stop condition output setup time

Data output setup time (master)

Data output setup time (slave)

Data output hold time

when IICX is 0, 12t

Output Timing

Figure 25-33