Status Register For Limit Test (Channel) - Agilent Technologies E5071C Manual

Status Register for Limit Test (channel)

Status Bit Definitions of the Questionable Limit Status Condition
Register
Bit Name
Position
0 Channel 15, 16 Limit Test
summary (questionable
limit extra status register
summary)
Description
Set to "1" while one of the
enabled bits in the
questionable limit extra
status event register is set to
"1."
Programming
1123