E5071C
Bit
Name
Position
0
Channel 15, 16 Bandwidth
test summary
(questionable bandwidth
limit extra status register
summary)
1
Channel 1 Bandwidth Test
Fail (questionable
bandwidth limit channel 1
status register summary)
2
Channel 2 Bandwidth Test
Fail (questionable
bandwidth limit channel 2
status register summary)
3
Channel 3 Bandwidth Test
Fail (questionable
bandwidth limit channel 3
status register summary)
4
Channel 4 Bandwidth Test
Fail (questionable
bandwidth limit channel 4
status register summary)
5
Channel 5 Bandwidth Test
Fail (questionable
bandwidth limit channel 5
status register summary)
6
Channel 6 Bandwidth Test
Fail (questionable
bandwidth limit channel 6
status register summary)
1140
Description
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
extra status event register is
set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 1 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 2 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 3 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 4 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 5 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 6 status event
register is set to "1."