Agilent Technologies E5071C Manual page 891

E5071C
0, 1 Not used
2 Error/Event
Queue
3 Questionable
Status Register
Summary
4 MAV (Message
Available)
5
Standard Event
Status Register
Summary
6 RQS
7 Operation Status
Register
Summary
Issuing the command will clear all bits from the status byte register.
*CLS
Status Bit Definitions of Standard Event Status Register
Bit Name
Position
0 Operation
Complete
1 Not used
1118
Always 0
Set to "1" if the error/event queue
contains data; reset to "0" when all
the data has been retrieved.
Set to "1" when one of the enabled
bits in the questionable status register
is set to "1."
Set to "1" when the output queue
contains data; reset to "0" when all
the data has been retrieved.
Set to "1" when one of the enabled
bits in the standard event status
register is set to "1."
Set to "1" when any of the status byte
register bits enabled by the service
request enable register is set to "1";
reset to "0" when all the data has
been retrieved through serial polling.
Set to "1" when one of the enabled
bits in the operational status register
is set to "1."
Description
Set to "1" upon completion of all
operations done by commands that
precede the *OPC? command.
Always 0