Agilent Technologies E5071C Manual page 899

E5071C
Status Bit Definitions of the Questionable Limit Extra Status
Condition Register
Bit Name
Position
0 Not used
1
Channel 15 Limit Test Fail
(questionable limit
channel 15 status register
summary)
2 Channel 16 Limit Test Fail
(questionable limit
channel 16 status register
summary)
3 - 15 Not used
Issuing the command will clear all bits from the questionable limit
*CLS
extra status event register.
1126
Description
Always 0
Set to "1" while one of the
enabled bits in the
questionable limit channel 15
status event register is set to
"1."
Set to "1" while one of the
enabled bits in the
questionable limit channel 16
status event register is set to
"1."
Always 0