7
Channel 7 Bandwidth Test
Fail (questionable
bandwidth limit channel 7
status register summary)
8
Channel 8 Bandwidth Test
Fail (questionable
bandwidth limit channel 8
status register summary)
9
Channel 9 Bandwidth Test
Fail (questionable
bandwidth limit channel 9
status register summary)
10
Channel 10 Bandwidth
Test Fail (questionable
bandwidth limit channel 10
status register summary)
11
Channel 11 Bandwidth
Test Fail (questionable
bandwidth limit channel 11
status register summary)
12
Channel 12 Bandwidth
Test Fail (questionable
bandwidth limit channel 12
status register summary)
13
Channel 13 Bandwidth
Test Fail (questionable
bandwidth limit channel 13
status register summary)
14
Channel 14 Bandwidth
Test Fail (questionable
bandwidth limit channel 14
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 7 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 8 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 9 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 10 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 11 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 12 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 13 status event
register is set to "1."
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
Programming
1141