System Control Registers - Infineon Technologies XC82x User Manual

Table 3-2 MDU Register Overview (cont'd)
Addr Register Name
B3 H MR1
MDU Result Register 1
B4 H MD2
MDU Operand Register 2
B4 H MR2
MDU Result Register 2
B5 H MD3
MDU Operand Register 3
B5 H MR3
MDU Result Register 3
B6 H MD4
MDU Operand Register 4
B6 H MR4
MDU Result Register 4
B7 H MD5
MDU Operand Register 5
B7 H MR5
MDU Result Register 5
3.4.5.3

System Control Registers

The system control SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-3 SCU Register Overview
Addr Register Name
RMAP = 0 or 1
8F H SYSCON0
System Control Register 0
RMAP = 0
F1 H SCU_PAGE
Page Register
RMAP = 0, PAGE 0
EE H NMICON
NMI Control Register
EF H EXICON0
External Interrupt Control
Register 0
User's Manual
Memory Organization, V 0.1
Bit
Reset: 00 H Bit Field
Type
Reset: 00 H Bit Field
Type
Reset: 00 H Bit Field
Type
Reset: 00 H Bit Field
Type
Reset: 00 H Bit Field
Type
Reset: 00 H Bit Field
Type
Reset: 00 H Bit Field
Type
Reset: 00 H Bit Field
Type
Reset: 00 H Bit Field
Type
Bit
Reset: 04 H Bit Field
Type
Reset: 00 H Bit Field
Type
Reset: 00 H Bit Field
Type
Reset: F0 H Bit Field
Type
7 6 5
7 6 5
0 IMOD
r
OP STNR
w w
0 NMI NMI NMI
ECC VDDP VDDC
r rw rw
EXINT3 EXINT2
rw rw
3-15
Memory Organization
4 3 2
DATA
rh
DATA
rw
DATA
rh
DATA
rw
DATA
rh
DATA
rw
DATA
rh
DATA
rw
DATA
rh
4 3 2
0 1
E
rw r r
0 PAGE
r
NMI NMI NMI
OCDS FLASH OSC
CLK
rw rw rw
EXINT1
rw
V1.0, 2010-02
XC82x
1 0
1 0
0 RMAP
r rw
rw
NMI
WDT
rw rw
EXINT0
rw