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The 16 bytes of RAM that occupy addresses from 20
of the internal data byte at 20
byte at 2F
has the bit address 7F
H
By default after reset, the stack pointer points to address 07
anywhere in the internal RAM.
RAM occupying direct addresses from 30
1.3.3.2
Internal Data Memory XRAM
The size of the internal XRAM is not fixed and varies depending on XC800 derivative.
The internal XRAM is mapped to both the external data space and the code space
because it can be accessed using both 'MOVX' and 'MOVC' instructions. When
accessed using the 8-bit MOVX instruction via register R0 or R1, the SFR XADDRH
must be initialized to specify the upper address byte.
The internal XRAM can be enabled or disabled. If disabled, external data memory can
be accessed in the address range of the internal XRAM, with activated external data
memory signals. If enabled, the external data memory signals are not generated when
the internal XRAM is accessed. Therefore, the corresponding ports can be used as
general purpose I/O in an application where there is no access to off-chip external data/
program memory.
1.3.3.3
External Data Memory
Up to 1 Mbyte of synchronous or asynchronous external data memory is supported.
External data memory extension, if supported by the XC800 derivative, is accomplished
with either the 4-bit Current Bank pointer (CB) or the 4-bit XRAM Bank pointer (MX),
selected by the MXM bit. The data is fetched from the 64-Kbyte block pointed to by CB
or MX. Some XC800 derivatives may not support external data memory.
1.3.4
Registers
All registers, except the program counter and the four general purpose register banks,
reside in the SFR area.
The lower 32 locations of the internal lower data RAM are assigned to four banks with
eight general purpose registers (GPRs) each. At any one time, only one of these banks
can be enabled by two bits in the program status word (PSW): RS0 (PSW.3) and RS1
(PSW.4). This allows fast context switching, which is useful when entering subroutines
or interrupt service routines. The eight general purpose registers of the selected register
bank may be accessed by register addressing. For indirect addressing modes, the
registers R0 and R1 are used as pointer or index register to address internal or external
memory.
User's Manual, V 0.1
has the bit address 00
H
.
H
to 7F
H
1-6
Fundamental Structure
to 2F
are bitaddressable. Bit 0
H
H
, while bit 7 of the internal data
H
. The stack may reside
H
can be used as scratch pad.
H
XC800
V 1.0, 2005-01
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