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MPC823e Instruction Set—andi.
andi.
Assembler Syntax
BIT
0
1
2
FIELD
28
BIT
16
17
18
FIELD
Definition
Operation
Description
B-18
andi.
rA,rS,UIMM
3
4
5
6
7
19
20
21
22
23
UIMM
AND Immediate
rA ← (rS) & ((16)0 || UIMM)
The contents of rS are ANDed with 0x0000 || UIMM and the
result is placed into rA.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
8
9
10
11
12
S
24
25
26
27
28
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
FORM
D
MOTOROLA
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