Agilent Technologies 8960 10 Series Reference Manual page 515

Setting Frame Trigger Parameters
Setting Frame Trigger Parameters
Frame Trigger Parameters
The frame trigger is a positive-going TTL compatible pulse that is one GSM bit wide, it is aligned to the
downlink TDMA frame timing. The test set provides a frame trigger for synchronizing other test equipment to
a measurement it is available at the rear-panel TRIG OUT connector.
The frame trigger has 3 parameters that the user must set. See "SYSTem:FTRigger" on page 490.
• External Trigger State (on or off)
• External Trigger Timeslot (0 to 7)
• External Trigger Bit (0 to 1250)
Examples
External Trigger State
OUTPUT 714;"SYSTEM:FTRIGGER:STATE ON"
would set the external frame trigger ON.
External Trigger Timeslot
OUTPUT 714;"SYSTEM:FTRIGGER:TSLOT 3"
would cause external frame trigger pulses to align with timeslot three.
External Trigger Bit
OUTPUT 714;"SYSTEM:FTRIGGER:BIT 100"
would cause external frame trigger pulses to occur 100 bits after bit 0 of the selected timeslot.
Operating Considerations
Each frame is made up of 8 time slots. Time slots are defined in "ETSI GSM 05.10 Ver. 4.9.0 Section 5. Time
slots 0 and 4 are 157 bit periods long, time slots 1, 2, 3, 5, 6, 7 are 156 bit periods long, the average time slot is
156.25 bits in duration. The external trigger timeslot can be set to any time slot 0 through 7, the external
trigger bit position can be set from 0 through 1250. If the trigger bit position is set to 1250, that is one full
frame beyond the setting of the external trigger timeslot, (156.25 * 8 = 1250).
When the cell activated state is OFF, the frame trigger output is disabled (set to 0 volts) since there is no
reference downlink TDMA frame structure available. However, the frame trigger state is not affected when
there are changes to cell activated state.
The frame trigger can be set manually from the system configuration screen by pressing the External Trigger
Setup soft key.
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