Agilent Technologies 8960 10 Series Reference Manual page 145

Status Subsystem Overview
Condition Register
A condition is a test set state that is either TRUE or FALSE (a GPIB command error has occurred or a GPIB
command error has not occurred). Each bit in a Condition Register is assigned to a particular test set state. A
Condition Register continuously monitors the hardware and firmware states assigned to it. There is no
latching or buffering of any bits in a Condition Register; it is updated in real time. Condition Registers are
read-only. Condition Registers in the test set are 16 bits long and may contain unused bits. All unused bits
return a zero value when read.
Some status register groups do not implement Condition registers for certain test set conditions. In the tables
labeled "Bit Definitions", these conditions are indicated by the word "NO" in the column labeled "Is Condition
Register Implemented?".
Transition Filters In the test set, the Transition Filters are implemented as two registers: a 16-bit positive
transition (PTR) register and a 16-bit negative transition (NTR) register.
For each bit in the Condition Register, a Transition Filter bit determines the state transitions which will set a
corresponding bit in the Event Register. Transition Filters may be set to pass positive transitions (PTR),
negative transitions (NTR) or either (PTR or NTR). A positive transition refers to a condition bit which has
changed from 0 to 1. A negative transition refers to a condition bit which has changed from 1 to 0.
A positive transition of a bit in the Condition register will be latched in the Event Register if the corresponding
bit in the positive transition filter is set to 1. A positive transition of a bit in the Condition register will not be
latched in the Event Register if the corresponding bit in the positive transition filter is set to 0.
A negative transition of a bit in the Condition register will be latched in the Event Register if the
corresponding bit in the negative transition filter is set to 1. A negative transition of a bit in the Condition
register will not be latched in the Event Register if the corresponding bit in the negative transition filter is set
to 0. Either transition (PTR or NTR) of a bit in the Condition Register will be latched in the Event Register if
the corresponding bit in both transition filters is set to 1. No transitions (PTR or NTR) of a bit in the Condition
Register will be latched in the Event Register if the corresponding bit in both transition filters is set to 0.
Transition Filters are read-write.
Transition Filters are unaffected by a *CLS (clear status) command.
Transitions Filters are set to pass positive transitions (all 16 bits of the PTR register are set to 1 and all 16 bits
of the NTR register are set to 0) at power on or after receiving the *RST (reset) command.
Event Register The Event Register captures bit-state transitions in the Condition Register as defined by the
Transition Filters. Each bit in the Event Register corresponds to a bit in the Condition Register, or if there is
no Condition Register/Transition Filter combination, each bit corresponds to a specific condition in the test
set. Bits in the Event Register are latched, and, once set, they remain set until cleared by a query of the Event
Register or a *CLS (clear status) command. This guarantees that the application can't miss a bit-state
transition in the Condition Register. There is no buffering; so while an event bit is set, subsequent transitions
in the Condition Register corresponding to that bit are ignored. Event Registers are read-only. Event Registers
in the test set are either 8 or 16 bits long and may contain unused bits. All unused bits return a zero value
when read.
Event Enable Register The Event Enable Register defines which bits in the Event Register will be used to
generate the Summary Message. Each bit in the Enable Register has a corresponding bit in the Event
Register. The test set logically ANDs corresponding bits in the Event and Enable registers and then performs
an inclusive OR on all the resulting bits to generate the Summary Message. By using the enable bits the
application program can direct the test set to set the Summary Message to the 1 or TRUE state for a single
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