Byte Mapping - Xilinx RocketIO User Manual

Byte Mapping

Table 1-8: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND,
and GT_XAUI (Continued)
Attribute
RX_LOS_INVALID_INCR
RX_LOS_THRESHOLD
RX_LOSS_OF_SYNC_FSM
SERDES_10B
TERMINATION_IMP
TX_BUFFER_USE
TX_CRC_FORCE_VALUE
TX_CRC_USE
TX_DATA_WIDTH
TX_DIFF_CTRL
TX_PREEMPHASIS
Notes:
1. Modifiable attribute for specific primitives.
2. Depends on primitive used: either 1, 2, or 4.
3. CRC_EOP and CRC_SOP are not applicable for this primitive.
Byte Mapping
Most of the 4-bit wide status and control buses correlate to a specific byte of TXDATA or RXDATA.
This scheme is shown in
data path width needed for the GT_CUSTOM. All other primitives with specific data width paths
and all byte-mapped ports are affected by this situation. For example, a 1-byte wide data path has
only 1-bit control and status bits (TXKERR[0]) correlating to the data bits TXDATA[7:0]. Footnote
3
Table 1-9: Control/Status Bus Association to Data Bus Byte Paths
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
Default
GT_FIBRE_CHAN
1
4
TRUE
FALSE
50
TRUE
11010110
FALSE
N
500
0
Table
in Table 1-5 shows the ports that use byte mapping.
Control/Status Bit
[0]
[1]
[2]
[3]
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Default
GT_INFINIBAND
(1)
1
(1)
4
(1)
TRUE
(1)
FALSE
(1)
50
TRUE
(1)
11010110
(1)
FALSE
(2)
N
(1)
500
(1)
0
1-9. This creates a way to tie all the signals together regardless of the
Data Bits
[7:0]
[15:8]
[23:16]
[31:24]
Default
GT_XAUI
(1)
1
(1)
4
(1)
TRUE
(1)
FALSE
(1)
50
TRUE
(1)
11010110
(1)
FALSE
(2)
N
(1)
500
(1)
0
R
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
37