Enabling 64B/66B Mode; Tx Raw Mode; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Enabling 64B/66B Mode

Follow these steps to enable the 64B/66B mode in the GTH transmitter:
1.
2.
3.
4.

TX Raw Mode

Functional Description

The GTH transceiver provides another datapath mode for non-encoded applications or
when the user wants to bypass the 8B/10B and 64B/66B blocks.

Ports and Attributes

Table 3-9
Table 3-9: TX Raw Mode Ports
Port Dir
TXCTRL0[7:0]
TXCTRL1[7:0]
TXCTRL2[7:0]
TXCTRL3[7:0]
TXDATA0[63:0]
TXDATA1[63:0]
TXDATA2[63:0]
TXDATA3[63:0]
TXDATAMSB0[7:0]
TXDATAMSB1[7:0]
TXDATAMSB2[7:0]
TXDATAMSB3[7:0]
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Set PCS_MODE_LANE<n>[3:0] to 4'b0001.
Set PCS_RESET_LANE<n> to 0xF3FE.
Set PCS_RESET_1_LANE<n>[1:0] to 2'b10.
Set TX_FABRIC_WIDTH<n> to "6466."
defines the TX raw mode ports.
Clock Domain
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
www.xilinx.com
Description
These inputs indicate control of TXDATA<n> or they are used as
an extension of TXDATA<n> depending on the mode selected in
the transmitter datapath:
8B/10B: These inputs are asserted when TXDATA<n> is an
8B/10B K character.
TXCTRL<n>[7] corresponds to TXDATA<n>[63:56]
TXCTRL<n>[6] corresponds to TXDATA<n>[55:48]
TXCTRL<n>[5] corresponds to TXDATA<n>[47:40]
TXCTRL<n>[4] corresponds to TXDATA<n>[39:32]
TXCTRL<n>[3] corresponds to TXDATA<n>[31:24]
TXCTRL<n>[2] corresponds to TXDATA<n>[23:16]
TXCTRL<n>[1] corresponds to TXDATA<n>[15:8]
TXCTRL<n>[0] corresponds to TXDATA<n>[7:0]
64B/66B: These inputs are 64B/66B control bits.
Raw mode: These inputs are used as part of TXDATA<n>[71:64].
This input bus is the transmit data bus of the transmit interface
from the FPGA.
This bus extends the transmit data bus as TXDATA<n>[79:72].
TX Raw Mode
89