Byte Mapping; Clocking; Clock Signals; Table 3-5: Control/Status Bus Association To Data Bus Byte Paths - Xilinx RocketIO User Manual

R

Byte Mapping

Most of the 4-bit wide status and control buses correlate to a specific byte of the TXDATA
or RXDATA. This scheme is shown in
together regardless of the data path width needed for the GT_CUSTOM. All other
primitives with specific data width paths and all byte-mapped ports are affected by this
situation. For example, a 1-byte wide data path has only 1-bit control and status bits
(TXKERR[0]) correlating to the data bits TXDATA[7:0]. Note
that use byte mapping.

Table 3-5: Control/Status Bus Association to Data Bus Byte Paths

Clocking

Clock Signals

There are five clock inputs into each RocketIO transceiver instantiation
is a clock generated from an external source. REFCLK is connected to the REFCLK of the
RocketIO transceiver. It also clocks a Digital Clock Manager (DCM) to generate all of the
other clocks for the gigabit transceiver. Typically, TXUSRCLK = RXUSRCLK and
TXUSRCLK2 = RXUSRCLK2. The transceiver uses one or two clocks generated by the
DCM. As an example, the USRCLK and USRCLK2 clocks run at the same speed if the 2-byte
data path is used. The USRCLK must always be frequency-locked to the reference clock,
REFCLK of the RocketIO transceiver.

Table 3-6: Clock Ports

Clock I/Os
(1)
BREFCLK Input
(1)
BREFCLK2 Input
RXRECCLK Output
REFCLK Input
REFCLK2 Input
REFCLKSEL Input
RXUSRCLK Input
TXUSRCLK Input
RXUSRCLK2 Input
38
Control/Status Bit
[0]
[1]
[2]
[3]
NOTE: The REFCLK must be at least 40 MHz (full-rate operation only; 62.2 MHz for half-rate
operation) with a duty cycle between 45% and 55%, and should have a frequency stability of
100 ppm or better, with jitter as low as possible. Module 3 of the Virtex-II Pro data sheet gives
further details.
Reference clock used to read the TX FIFO and multiplied by 20 for parallel-to-serial
conversion (20X)
Alternative to BREFCLK
Recovered clock (from serial data stream) divided by 20
Reference clock used to read the TX FIFO and multiplied by 20 for parallel-to-serial
conversion (20X)
Reference clock used to read the TX FIFO and multiplied by 20 for parallel-to-serial
conversion (20X)
Selects which reference clock is used. 0 selects REFCLK; 1 selects REFCLK2.
Clock from FPGA used for reading the RX Elastic Buffer. Clock signals CHBONDI and
CHBONDO into and out of the transceiver. This clock is typically the same as
TXUSRCLK.
Clock from FPGA used for writing the TX Buffer. This clock must be frequency locked
to REFCLK for proper operation.
Clock from FPGA used to clock RX data and status between the transceiver and FPGA
fabric. The relationship between RXUSRCLK2 and RXUSRCLK depends on the width
of the receiver data path. RXUSRCLK2 is typically the same as TXUSRCLK2.
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Chapter 3: Digital Design Considerations
Table 3-5. This creates a way to tie all the signals
3 in
Data Bits
[7:0]
[15:8]
[23:16]
[31:24]
Description
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
Table 3-1 shows the ports
(Table 3-6). REFCLK