Figure 3-5: Txoutclk 1:1:1; Figure 3-6: Rxrecclk 1:1:1 - Xilinx RocketIO X User Manual
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Also See for RocketIO X:
- User manual (152 pages) ,
- User manual (156 pages) ,
- User manual (124 pages)
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Clock Domain Architecture
TXOUTCLK
USRCLK
USRCLK2 and
User Logic
RXRECCLK*
USRCLK
USRCLK2 and
User Logic
*RXRECCLK should only drive the receive clocks
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
Figure 3-5: TXOUTCLK 1:1:1
DCMs are optional
Using BREFCLK 1:1:1
for TX
Figure 3-6: RXRECCLK 1:1:1
www.xilinx.com
1-800-255-7778
DCM
CLKIN
CLK0
BUFG
CLKDV
CLKFX
CLKFB
User
TX & RX
Logic
DCM is optional
DCM
CLKIN
CLK0
BUFG
CLKDV
CLKFX
CLKFB
User
TX
Logic
RX
DCM
CLKIN
CLK0
BUFG
CLKDV
CLKFX
CLKFB
UG035_CH3_13_060304
R
GT10
BREFCLK
TXOUTCLK
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
TXDATA
RXDATA
RXRECCLK
UG035_CH3_08_060304
GT10
BREFCLK
TXOUTCLK
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
TXDATA
RXDATA
RXRECCLK
77
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