Clocking From An External Source; Clocking From A Neighboring Gth Quad - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features
Table 2-5
.
Table 2-5: Reference Clock Selection Attributes

Clocking from an External Source

Each GTH Quad has a dedicated pin that can be connected to an external clock source. To
use these pins, an IBUFDS_GTHE1 primitive is instantiated. In the user constraints file
(UCF), the IBUFDS_GTHE1 input pins are constrained to the locations of the dedicated
clock pins for the GTH Quad. In the design, the output of the IBUFDS_GTHE1 primitive is
connected to the REFCLK input port. The locations of the dedicated pins for all GTH
Quads are documented in
Figure 2-2
board.
X-Ref Target - Figure 2-2

Clocking from a Neighboring GTH Quad

The external reference clock from one GTH Quad can be used to drive the REFCLK input
port of the neighboring GTH Quad. The example in
GTH Quad to clock one neighbor above and one neighbor below. A GTH Quad shares its
clock with its neighbors using the dedicated clock routing resources.
46
defines the reference clock selection attributes.
Attribute Type
PLL_CFG2 16-bit Hex
shows a differential GTH clock pin pair sourced by an external oscillator on the
MGTREFCLKP
MGTREFCLKN
Figure 2-2: Single GTHE1_QUAD Clocked Externally
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Reserved. Use the recommended values from the
Virtex®-6 FPGA GTH Transceiver Wizard.
Implementation, page 31.
I
O
IB
Virtex-6 FPGA GTH Transceivers User Guide
Description
GTHE1_QUAD
REFCLK
UG371_c2_01_082609
Figure 2-3 uses the clock from one
UG371 (v2.0) February 16, 2010