Chapter 2: Clocking, Timing, And Resets; Clock Distribution; Column; Tile - Xilinx Virtex-4 RocketIO User Manual

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Clocking, Timing, and Resets

Clock Distribution

The RocketIO™ MGT clock distribution has changed from previous generations to
support the columnar architecture of the Virtex®-4 devices.

Column

A column consists of multiple MGT tiles containing two MGTs each. The MGT tile contains
routing for the PLL reference clocks and the clocks that are derived from the PLLs. The
clocks derived from the PLLs are forwarded to the FPGA global clock resources. Two low-
jitter reference clock trees (SYNCLK1 and SYNCLK2) run the entire length of the column.
These SYNCLKs have the ability to route a clock completely up and down a column or to
become tile local clocks. See
more details.

Tile

In a tile, each PLL can select its own RX reference clock and a shared TX reference clock.
This is because a single PLL is shared by the transmitters, whereas each receiver has an
independent PLL and CDR.

MGT

In a Virtex-4 device, there are eleven clock inputs into each Virtex-4 RocketIO MGT
instantiation. There are three reference inputs to choose from:
•
•
The attributes in
three PLLs in a tile. These clocks are routed differentially in the FPGA to provide better
signal integrity.
The reference clock inputs should never be driven from a DCM because its output jitter is
too high. Only one of these reference clocks is needed to run the MGT. However, multiple
clocks can be used to implement multi-rate designs.
Most of the four user clocks (TXUSRCLK, TXUSRCLK2, RXUSRCLK, and RXUSRCLK2)
can be created within the MGT block without the use of a DCM. However, reference clocks
or several MGT clock outputs can be used to drive DCMs, which in turn create the
necessary clocks. Only DCM outputs CLK0 and DV are suitable; the FX output is not
supported. The clocking attributes and serial speed determine the reference clock speed, as
shown in
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
"GT11CLK_MGT and Reference Clock Routing," page 63
Two column SYNCLKs, which drive the REFCLK1 and REFCLK2 inputs of the MGTs
One tile local GREFCLK (for applications below 1 Gb/s).
Figure 2-1 and
Table 1-3, "MGT Protocol Settings," page
www.xilinx.com
Table 2-3 show how to select the reference clock for the
37.
Chapter 2
for
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