Chapter 2: Digital Design Considerations; Clocking; Clock Signals - Xilinx RocketIO User Manual

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Digital Design Considerations

Clocking

Clock Signals

There are eight clock inputs into each RocketIO transceiver instantiation
REFCLK and BREFCLK are reference clocks generated from an external source and
presented to the FPGA as differential inputs. The reference clocks connect to the REFCLK
or BREFCLK ports of the RocketIO multi-gigabit transceiver (MGT). While only one of
these reference clocks is needed to drive the MGT, BREFCLK or BREFCLK2 must be used
for serial speeds of 2.5 Gb/s or greater. (See
To clock the serial data, the PLL architecture for the transceiver uses the reference clock as
the interpolation source. Removing the reference clock stops the RX and TX PLLs from
working. Therefore, a reference clock must be provided at all times. This is especially
important at the end of configuration when the PMA portion of the MGT requires a
reference clock in order to properly initialize. If a reference clock is not available at this
point, the user should toggle the POWERDOWN pin when the reference clock becomes
available to ensure the PMA is properly initialized.
The reference clock also clocks a Digital Clock Manager (DCM) or a BUFG to generate all of
the other clocks for the MGT. Never run a reference clock through a DCM, since unwanted
jitter will be introduced. Any additional jitter on the reference clock will be transferred to
the transceiver's RX and TX serial I/O.
It is recommended that all reference clock sources into the FPGA be LVDS or LVPECL
IBUFGDS. The DCI or DT attributes of LVDS are optional. Refer to the
FPGA User Guide
discussion of IBUFGDS and other available I/O primitives. Also see section
Clock" in Chapter 3
Typically, TXUSRCLK = RXUSRCLK and TXUSRCLK2 = RXUSRCLK2. The transceiver
uses one or two clocks generated by the DCM. As an example, USRCLK and USRCLK2
clocks run at the same speed if the 2-byte data path is used. The USRCLK must always be
frequency-locked to the reference clock of the RocketIO transceiver when SERDES_10B =
FALSE (full-rate operation).
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
(Chapter 3, "Design Considerations") for a complete listing and
of this Guide.
Note:
The reference clock must be at least 50 MHz (for full-rate operation only; 60 MHz for half-
rate operation) with a duty cycle between 45% and 55%, and should have a frequency stability of
www.xilinx.com
Chapter 2
"BREFCLK," page 41.)
Virtex-II Pro Platform
(Table 2-1).
"Reference
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