Transmit Fabric Clocking Use Model For Tx Buffer Bypass - Xilinx Virtex-6 FPGA User Manual

For phase alignment to be effective, TXUSRCLK and TXUSRCLK2 for all GTX transceivers
must come from the same source and must be routed through a low-skew clocking
resource (such as BUFG,BUFR or MMCM). When TXOUTCLK is used as the clock source
in TX buffer bypass mode, TXOUTCLK_CTRL must select either TXPLLREFCLK_DIV1 or
TXPLLREFCLK_DIV2. Refer to
page 136
driven for low-skew operation.

Transmit Fabric Clocking Use Model for TX Buffer Bypass

The system margin in TX Buffer Bypass mode depends on the following:
•
•
Table 3-21
function of the line rate and the internal Data Width. To enhance the system margin for
better compensation to Temperature and/or Voltage drift, these requirements must be met.
Table 3-21: Required Clocking Use Model When bypassing the TX Buffer as a
Function of the Line Rate and the internal Data Width
1. MMCM must be placed in the same clock region as the driving GTX. For details about placement
FPGA TX Interface
Figure 3-5
Figure 3-6
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
for additional examples on how TXUSRCLK and TXUSRCLK2 signals should be
TXUSRCLK frequency (See
Clocking resources used to generate TXUSRCLK from TXOUTCLK (BUFG, BUFR or
MMCM)
describes the required clocking use model when bypassing the TX Buffer as a
Internal Data
Line Rate (Gb/s)
Width
4.2
20-bit
 5.8
20-bit
 6.2
20-bit
 6.6
20-bit
 4.2
16-bit
4.6
16-bit
 4.9
16-bit
 6.6
16-bit
constraints and restrictions on clocking resources (BUFG, BUFR, MMCM, etc.), refer to the Virtex-
6 FPGA Clocking Resources User Guide.
describes these clocking use models in detail. Figures
describe the clocking use model with BUFG and BUFR. Figures
describe the clocking use model with MMCM.
www.xilinx.com
Figure 3-5, page 134, Figure 3-6, page
Equation 3-1)
Device
 240T
BUFG, BUFR, MMCM
 240T
BUFR, MMCM
 240T
MMCM
 240T
MMCM
 240T
BUFG, BUFR, MMCM
 240T
BUFR, MMCM
 240T
MMCM
 240T
MMCM
TX Buffer Bypass
135, and Figure 3-7,
Clocking Use Model
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Figure 3-2 and
Figure 3-3 and
161