Pll; Functional Description - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features

PLL

Functional Description

Each GTHE1_QUAD primitive has one PLL block that is shared between the four lanes
within the Quad. Each lane in the GTH Quad has separate dividers for the transmitter and
the receiver, which allow each transmitter and receiver to operate in different
divided-down line rates based on the VCO frequency. The PLL in one GTHE1_QUAD
primitive cannot be shared with another GTH Quad.
The PLL has an operating range from 4.96 GHz to 5.591 GHz with the lane divider, which
can divide the output of the PLL by one or four.
and PLL settings in the GTH transceiver.
Table 2-6: Supported Line Rates per TX and RX Lane Divider Settings
Figure 2-4
recommended for optimal jitter performance. The feedback divider determines the VCO
multiplication and the PLL output frequency.
48
TX and RX PLL Lane Divider
1
4
illustrates the PLL architecture. A low phase noise PLL input clock is
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Table 2-6 shows the supported line rate
Line Rate Range (Gb/s)
9.920 – 11.182
2.48 – 2.58
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010