Application Notes; Serial Interfaces; Xapp648: Serial Backplane Interface To A Shared Memory - Xilinx RocketIO User Manual

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Application Notes

XAPP572: A 3/4/5/6X Oversampling Circuit for 200 Mb/s to 1000 Mb/s

Serial Interfaces

High-speed Serializer/Deserializer (SERDES) devices (1 Gb/s and higher) are often
analog-based and tuned for a particular frequency range. If a design requires using the
SERDES for lower-rate applications, such as interfacing with legacy systems, an
oversampling circuit must be attached to the "back end" of the SERDES to extend the
SERDES to the lower frequency ranges. The circuit works by oversampling the incoming
serial data stream, evaluating data transition locations, and extracting valid data bits from
the oversampled data.
The oversampling module described in this application note performs 3/4/5/6X
oversampling. The oversampling ratio is selectable during operation to facilitate multi-rate
applications. It is designed to accept 20 bits of oversampled data and to output 10 bits of
extracted data to the user interface. This module can be used with the Virtex-II Pro™
RocketIO™ Multi-Gigabit Transceiver (MGT) to achieve line rates of 200 Mb/s to
1000 Mb/s. When using the Virtex-II Pro RocketIO MGT, sinusoidal input jitter tolerance
exceeds 0.55 UI(1) for 3/4/5X oversampling when tested with the PRBS-23 data pattern,
and over 0.38 UI(2) when tested with the SONET CID data pattern.
Characterization reports and descriptions of the oversampling techniques are available in
the Xilinx SPICE Lounge
request.htm) in a document titled, RocketIO 3X-Oversampling Logic Block Characterization:
Test Report.
For applications requiring line rates less than 200 Mb/s, using Virtex-II Pro X 10 Gb/s
RocketIO X MGTs, or implementing SD-SDI functionality, contact the Xilinx support
hotline for oversampling circuits that are specially designed and optimized for each of
these applications.

XAPP648: Serial Backplane Interface to a Shared Memory

This application note utilizes the Virtex-II Pro™ RocketIO™ transceivers and the Xilinx
Aurora Protocol Engine to provide a multi-ported interface to a shared memory system in
a backplane environment. Multiprocessor systems are often encountered in backplane
systems, and distributed processing applications require access to a shared memory across
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
(http://support.xilinx.com/support/software/spice/spice-
www.xilinx.com
Appendix C
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