Power-Down Features For Pci Express Operation; Loopback; Functional Description - Xilinx Virtex-6 FPGA User Manual

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Refer to

Power-Down Features for PCI Express Operation

The GTX transceiver implements all of the functions needed for power-down states
compatible with those defined in the PCI Express and PIPE specifications. When
implementing PCI Express compatible power control, the following conditions must be
met:
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Table 2-15: TX and RX Power States for PCI Express Operation
TXPOWERDOWN[1:0]
and TXDETECTRX
RXPOWERDOWN[1:0]
00 (P0 State)
01 (P0s state)
(1)
10 (P1 state)
(1)
11 (P2 state)
Notes:
1. Transmitter only. The P1 and P2 power states are not supported by the receiver.

Loopback

Functional Description

Loopback modes are specialized configurations of the transceiver datapath where the
traffic stream is folded back to the source. Typically, a specific traffic pattern is transmitted
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
RXPLLPOWERDOWN must be tied Low.
RXPOWERDOWN[0] and RXPOWERDOWN[1] must be tied Low.
RX Buffer Bypass, page 231
RXPOWERDOWN[1] must be tied Low.
RXPOWERDOWN[0] must be tied to TXPOWERDOWN[0].
The POWERDOWN[1:0] signal defined by the PIPE 2.0 Specification must be
connected to TXPOWERDOWN[1:0].
The TXPLLPOWERDOWN and RXPLLPOWERDOWN ports must be tied Low.
TXELECIDLE
0 0
0 1
1 0
1 1
Don't Care 0
1
Don't Care 0
0 1
1 1
Don't Care 0
1
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for more information.
Description
The PHY is transmitting data. The Media Access Layer
(MAC) provides data bytes to be sent every clock cycle.
The PHY is not transmitting and is in the electrical idle state.
The PHY goes into loopback mode.
Not permitted.
The MAC must always put the PHY into the electrical idle
state while in P0s state. The PHY behavior is undefined if
TXELECIDLE is deasserted while in P0s or P1.
The PHY is not transmitting and is in the electrical idle state.
Not permitted. The MAC must always put the PHY into the
electrical idle state while in P1. The PHY behavior is
undefined if TXELECIDLE is deasserted while in P0s or P1.
The PHY is idle.
The PHY does a receiver detection operation.
The PHY transmits beacon signaling
The PHY is idle.
Loopback
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